Development of wafer thinning and double-sided bumping technologies for the three-dimensional stacked LSI

Abstract

The three-dimensional (3D) chip stacking technology has been developed extensively recently for the next generation packaging technology. The technology includes thorough electrode fabrication, wafer thinning, wafer backside processing, testing, and chip stacking. Wafer thinning and wafer backside processing are important technologies among them, because these technologies accommodate small and thin form factor, enable thin chip stacking, and enhances electrical and mechanical reliability of the stacked module. In this paper, novel technologies of wafer thinning and wafer backside processes that include insulation film formation and bumping on the backside of the thinned wafer are described.