Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008335
Y. Ling
Realizing the increasing importance of the PCB (printed circuit board) current carrying capacities in PC (personal computer) applications, this paper addresses the DC and AC current carrying capacity problems. The classic Fourier series method is used for both two and one-dimensional analyses. But for the simple case of a single conductor arbitrarily located along the PCB length, a direct analytical solution is given without using the Fourier series. It is found that the 1-D and 2-D solutions yield an almost identical result for a typical PC motherboard. Many inside understandings are gained by revealing the impact on the current carrying capacity of various parameters such as the time, conductor thickness and width, allowable temperature rise, heat transfer coefficient, PCB copper volume percentage, PCB length and thickness, as well as the number of traces and their separations. The time constant of a PCB in a typical PC application is in the order of 100 seconds. Thus, the PCB can hardly have time to thermally respond to the AC components of I/sup 2/ even for a frequency as low as 1 hertz. Thus for any practical purpose, the conductor traces can be sized using the mean square value of the current, just based on the DC analysis. The conductor trace location along the PCB thickness has very little impact on its current carrying capacity and there shouldn't be any derating factor for internal traces in their current carrying capacities. The IPC (1998) practice of derating the external trace current carrying capacity by 50% for the internal traces should be stopped. However, the location of a conductor trace along the PCB length does have impact. The trace located at the edge of a PCB will have a lower current carrying capacity than the trace at the center. The current carrying capacity is proportional to the square root of the trace thickness, and approximately proportional to the square root of the allowable temperature rise. But the dependencies of the PCB current carrying capacity to the trace width, heat transfer coefficient, copper volume percentage, PCB length and thickness, as well as the number traces and their separations are rather complicated, governed by the relevant equations derived in this paper. The PCB current carrying capacity design charts applicable to typical desktop PC applications are presented. They provide a tool to conservatively estimate the conductor size necessary to carrying the required current level. But more precisely predicting the current carrying capacity would require experiments that simulate the PC motherboard application conditions to determine the critical properties such as the heat transfer coefficient and the PCB equivalent thermal conductivity. This will be the future work.
{"title":"On current carrying capacities of PCB traces","authors":"Y. Ling","doi":"10.1109/ECTC.2002.1008335","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008335","url":null,"abstract":"Realizing the increasing importance of the PCB (printed circuit board) current carrying capacities in PC (personal computer) applications, this paper addresses the DC and AC current carrying capacity problems. The classic Fourier series method is used for both two and one-dimensional analyses. But for the simple case of a single conductor arbitrarily located along the PCB length, a direct analytical solution is given without using the Fourier series. It is found that the 1-D and 2-D solutions yield an almost identical result for a typical PC motherboard. Many inside understandings are gained by revealing the impact on the current carrying capacity of various parameters such as the time, conductor thickness and width, allowable temperature rise, heat transfer coefficient, PCB copper volume percentage, PCB length and thickness, as well as the number of traces and their separations. The time constant of a PCB in a typical PC application is in the order of 100 seconds. Thus, the PCB can hardly have time to thermally respond to the AC components of I/sup 2/ even for a frequency as low as 1 hertz. Thus for any practical purpose, the conductor traces can be sized using the mean square value of the current, just based on the DC analysis. The conductor trace location along the PCB thickness has very little impact on its current carrying capacity and there shouldn't be any derating factor for internal traces in their current carrying capacities. The IPC (1998) practice of derating the external trace current carrying capacity by 50% for the internal traces should be stopped. However, the location of a conductor trace along the PCB length does have impact. The trace located at the edge of a PCB will have a lower current carrying capacity than the trace at the center. The current carrying capacity is proportional to the square root of the trace thickness, and approximately proportional to the square root of the allowable temperature rise. But the dependencies of the PCB current carrying capacity to the trace width, heat transfer coefficient, copper volume percentage, PCB length and thickness, as well as the number traces and their separations are rather complicated, governed by the relevant equations derived in this paper. The PCB current carrying capacity design charts applicable to typical desktop PC applications are presented. They provide a tool to conservatively estimate the conductor size necessary to carrying the required current level. But more precisely predicting the current carrying capacity would require experiments that simulate the PC motherboard application conditions to determine the critical properties such as the heat transfer coefficient and the PCB equivalent thermal conductivity. This will be the future work.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114965762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008310
Lirong Zheng, H. Tenhunen
This paper reports the development process and the updated information for the course Mixed Signal System Design, in the curriculums of system-on-chip master program and Ph.D. program in electronic system design at the Royal Institute of Technology (KTH), Stockholm, Sweden. The course aims to provide a unified view of physical system architectures from chip, circuit board, to cabinets. The course focuses on basic theory and analysis methods as well as design practice for high performance interconnections and packaging in such complex, mixed-signal end-products as mobile terminals and base-stations. Unlike many existing packaging courses, our course emphasizes physical performance constraints of interconnects and packaging and their dependencies on the underlying technologies, their impacts on the resulting system architectures and signal integrity. This is because our targeted students are chip and system designers rather than packaging experts. After this course, the students can choose an appropriate set of implementation technologies from semiconductor level to packaging and board level for their mixed signal end products, physically partition the system functionality across the packaging hierarchy with respect to mixed signal coupling constraints, perform physical performance estimation and trade-off analysis and define the appropriate physical architecture for system implementation.
{"title":"Mixed signal system design: a system integration and packaging course developed for chip and system designers","authors":"Lirong Zheng, H. Tenhunen","doi":"10.1109/ECTC.2002.1008310","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008310","url":null,"abstract":"This paper reports the development process and the updated information for the course Mixed Signal System Design, in the curriculums of system-on-chip master program and Ph.D. program in electronic system design at the Royal Institute of Technology (KTH), Stockholm, Sweden. The course aims to provide a unified view of physical system architectures from chip, circuit board, to cabinets. The course focuses on basic theory and analysis methods as well as design practice for high performance interconnections and packaging in such complex, mixed-signal end-products as mobile terminals and base-stations. Unlike many existing packaging courses, our course emphasizes physical performance constraints of interconnects and packaging and their dependencies on the underlying technologies, their impacts on the resulting system architectures and signal integrity. This is because our targeted students are chip and system designers rather than packaging experts. After this course, the students can choose an appropriate set of implementation technologies from semiconductor level to packaging and board level for their mixed signal end products, physically partition the system functionality across the packaging hierarchy with respect to mixed signal coupling constraints, perform physical performance estimation and trade-off analysis and define the appropriate physical architecture for system implementation.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115292966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008176
R. Kiumi, J. Yoshioka, F. Kuriyama, N. Saito, M. Shimoyama
For flip-chip packaging applications, a fine pitch bump process on LSI wafers is required due to increased chip circuit density, operating speed, and performance. Plating process is suitable for making the fine pitch bumps with high-speed deposition and high reliability. At the same time, lead-free processes, for electronic devices and components, are required to address environmental concerns. Also, high-speed bumping processes have to be developed for mass production, low cost, small footprint, and high throughput. Ebara has developed electroplating technologies for eutectic Sn-Pb solder, high lead solder, lead-free solder, and copper stud bumps on silicon wafers with higher deposition rates. The bumps were fabricated as column or mushroom type using resist plating masks, such as negative, positive spin-on, and dry film photo resists. The results show that Ebara's processes are suitable for mass production, with well-controlled bump geometry.
{"title":"Process development of electroplate bumping for ULSI flip chip technology","authors":"R. Kiumi, J. Yoshioka, F. Kuriyama, N. Saito, M. Shimoyama","doi":"10.1109/ECTC.2002.1008176","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008176","url":null,"abstract":"For flip-chip packaging applications, a fine pitch bump process on LSI wafers is required due to increased chip circuit density, operating speed, and performance. Plating process is suitable for making the fine pitch bumps with high-speed deposition and high reliability. At the same time, lead-free processes, for electronic devices and components, are required to address environmental concerns. Also, high-speed bumping processes have to be developed for mass production, low cost, small footprint, and high throughput. Ebara has developed electroplating technologies for eutectic Sn-Pb solder, high lead solder, lead-free solder, and copper stud bumps on silicon wafers with higher deposition rates. The bumps were fabricated as column or mushroom type using resist plating masks, such as negative, positive spin-on, and dry film photo resists. The results show that Ebara's processes are suitable for mass production, with well-controlled bump geometry.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115450195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008322
P. Svasta, D. Simion-Zanescu, C. Willi
One of the most used soldering processes for SMD components is the reflow process. For the PCBs one should expect the increasing of the components density and interconnection density together with the continuous reducing of component size and weight. It is well known how important it is for a proper soldering process to have the temperature distribution on the junction point between component pins and the corresponding pads. Mainly convection and radiation realize the temperature distribution in the reflow oven. Usual thermal conduction is treated to study the dissipation characteristics from a structure to the environment. In case of SMT assembly it is reversed, the influence of inside environment of a reflow oven acts on the assembled structure. The way of heat transfer and physical properties of the subassemblies are very important to obtain reliable product; "zero defects". The paper has two main goals. First, to present a simple method to realize a map of heaters according with the oven's geometrical profile. This is necessary for mathematical modeling, computing and/or simulation. In the second part this method will be emphasized.
{"title":"Thermal conductivity influence in SMT reflow soldering process","authors":"P. Svasta, D. Simion-Zanescu, C. Willi","doi":"10.1109/ECTC.2002.1008322","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008322","url":null,"abstract":"One of the most used soldering processes for SMD components is the reflow process. For the PCBs one should expect the increasing of the components density and interconnection density together with the continuous reducing of component size and weight. It is well known how important it is for a proper soldering process to have the temperature distribution on the junction point between component pins and the corresponding pads. Mainly convection and radiation realize the temperature distribution in the reflow oven. Usual thermal conduction is treated to study the dissipation characteristics from a structure to the environment. In case of SMT assembly it is reversed, the influence of inside environment of a reflow oven acts on the assembled structure. The way of heat transfer and physical properties of the subassemblies are very important to obtain reliable product; \"zero defects\". The paper has two main goals. First, to present a simple method to realize a map of heaters according with the oven's geometrical profile. This is necessary for mathematical modeling, computing and/or simulation. In the second part this method will be emphasized.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115731876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008326
S. Liong, C. Wong, W. Burgoyne
Generally, isotropically conductive adhesive formulations include epoxy resin as the polymeric matrix. Although epoxy has superior adhesion capability, its drawbacks include the tendency to absorb moisture and lack of reworkability (thermosetting polymer). In this study, a thermoplastic polymer with low moisture absorption (0.279wt%), called polyarylene ether (PAE2), is used in isotropically conductive adhesive (ICA) formulation. Previous research work by Lu et. al. (1999) showed that the moisture absorbed into epoxy caused galvanic corrosion, which results in the formation of metal oxide. By using a polymer with low moisture absorption, the amount of water present in ICA will be small, and the corrosion rate and formation of metal oxide can be reduced. However, previous measurements of contact resistance stability of PAE2-based ICA showed that they are not stable on all surface finishes. It was determined that for thermoplastic-based ICA, poor adhesion was the main mechanism for unstable contact resistance. Two methods of adhesion improvement are evaluated in this work. The first is to use coupling agents and the second is to blend the thermoplastic with epoxy. Both methods showed promise in improving the contact resistance stability of polyarylene ether based ICA.
{"title":"Adhesion improvement of thermoplastic isotropically conductive adhesive","authors":"S. Liong, C. Wong, W. Burgoyne","doi":"10.1109/ECTC.2002.1008326","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008326","url":null,"abstract":"Generally, isotropically conductive adhesive formulations include epoxy resin as the polymeric matrix. Although epoxy has superior adhesion capability, its drawbacks include the tendency to absorb moisture and lack of reworkability (thermosetting polymer). In this study, a thermoplastic polymer with low moisture absorption (0.279wt%), called polyarylene ether (PAE2), is used in isotropically conductive adhesive (ICA) formulation. Previous research work by Lu et. al. (1999) showed that the moisture absorbed into epoxy caused galvanic corrosion, which results in the formation of metal oxide. By using a polymer with low moisture absorption, the amount of water present in ICA will be small, and the corrosion rate and formation of metal oxide can be reduced. However, previous measurements of contact resistance stability of PAE2-based ICA showed that they are not stable on all surface finishes. It was determined that for thermoplastic-based ICA, poor adhesion was the main mechanism for unstable contact resistance. Two methods of adhesion improvement are evaluated in this work. The first is to use coupling agents and the second is to blend the thermoplastic with epoxy. Both methods showed promise in improving the contact resistance stability of polyarylene ether based ICA.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116630250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008187
R. Ulrich
A Web-based course in integrated passive technology is proposed, aimed at both the industrial user who must access stand-alone topics and at the university student who wants a comprehensive graduate-level course for academic credit. A brief description is given on how such a course would be organized along with an outline of suggested course topics. The bulk of this paper goes into the details of some of these topics to demonstrate why they are valuable to the understanding of integrated passive technology and to show how they might be presented in the course.
{"title":"Integrated passive component technology education project","authors":"R. Ulrich","doi":"10.1109/ECTC.2002.1008187","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008187","url":null,"abstract":"A Web-based course in integrated passive technology is proposed, aimed at both the industrial user who must access stand-alone topics and at the university student who wants a comprehensive graduate-level course for academic credit. A brief description is given on how such a course would be organized along with an outline of suggested course topics. The bulk of this paper goes into the details of some of these topics to demonstrate why they are valuable to the understanding of integrated passive technology and to show how they might be presented in the course.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117265699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008071
T. Budell, P. Clouser, J. Audet
This paper presents a comparison of simultaneous switching-output noise and skew measurements taken with a 0.12 /spl mu/m CMOS test chip on three flip-chip, multilayer-ceramic, single-chip modules (SCMs) having differing amounts of reference mesh and power-supply vias in the package under the chip outline. Missing reference mesh equates to poor current-return paths for signals traversing such package regions. Missing power-supply vias equate to increased supply inductance. The test chip has 732 individually programmable off-chip output buffers, each of which can be individually probed. The first package has full reference mesh under the chip. The second package has reference mesh only in the upper half of the package under the chip. The third package has essentially no reference mesh under the chip. Technology and design features of the chip and package test vehicles are described. Noise and delay measurement techniques and results are presented. The large number of off-chip output buffers enables a statistical view of transmitted noise and skew behavior as signal current-return paths are compromised. This analysis is graphically presented and discussed. Several types of simulations, including extracted loop inductance and full-wave simulation of coupling parameters, are presented. These simulations elucidate the large differences in measured transmitted noise and off-chip output buffer skew between the three packages.
本文介绍了一个0.12 /spl μ l /m CMOS测试芯片在三个倒装、多层陶瓷、单芯片模块(scm)上同时进行的开关输出噪声和倾斜测量的比较，这些模块在芯片外形下的封装中具有不同数量的参考网格和电源过孔。缺少参考网格相当于信号穿过这些封装区域的电流返回路径不佳。缺少电源过孔等于增加了电源电感。测试芯片有732个单独可编程的片外输出缓冲器，每个都可以单独探测。第一个封装在芯片下有完整的参考网格。第二种封装仅在芯片下方的封装上半部分有参考网格。第三个封装基本上没有芯片下的参考网格。介绍了芯片和封装测试车的技术和设计特点。介绍了噪声和时延测量技术及其结果。当信号电流返回路径受损时，大量的片外输出缓冲器可以统计传输噪声和歪斜行为。这一分析以图形形式呈现并进行了讨论。提出了几种仿真方法，包括提取环路电感和耦合参数的全波仿真。这些模拟说明了三种封装之间在测量传输噪声和片外输出缓冲倾斜方面的巨大差异。
{"title":"Comparison of simultaneous switching noise measurements using netlist compatible multilayer ceramic packages having variously compromised reference planes","authors":"T. Budell, P. Clouser, J. Audet","doi":"10.1109/ECTC.2002.1008071","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008071","url":null,"abstract":"This paper presents a comparison of simultaneous switching-output noise and skew measurements taken with a 0.12 /spl mu/m CMOS test chip on three flip-chip, multilayer-ceramic, single-chip modules (SCMs) having differing amounts of reference mesh and power-supply vias in the package under the chip outline. Missing reference mesh equates to poor current-return paths for signals traversing such package regions. Missing power-supply vias equate to increased supply inductance. The test chip has 732 individually programmable off-chip output buffers, each of which can be individually probed. The first package has full reference mesh under the chip. The second package has reference mesh only in the upper half of the package under the chip. The third package has essentially no reference mesh under the chip. Technology and design features of the chip and package test vehicles are described. Noise and delay measurement techniques and results are presented. The large number of off-chip output buffers enables a statistical view of transmitted noise and skew behavior as signal current-return paths are compromised. This analysis is graphically presented and discussed. Several types of simulations, including extracted loop inductance and full-wave simulation of coupling parameters, are presented. These simulations elucidate the large differences in measured transmitted noise and off-chip output buffer skew between the three packages.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123580526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008203
V. Kripesh, M. Sivakumar, L. A. Lim, R. Kumar, M. Iyer
This study investigates wire bonding impact on low-k dielectric material used in dual damascene copper integrated circuits. The paper focuses on wire bond process optimization required for devices with soft low-k dielectric material compared to device with hard standard silicon dioxide dielectric. A fine pitch (60 /spl mu/m bond pitch) wire bonding process was established on test vehicles with SiO/sub 2/ and low-k SiLK dielectrics. All wire bond process parameters were established on the SiO/sub 2/ test vehicle. The process optimization was carried out with emphasis on free air ball formation, first bond and wedge bond. Optimized process parameters were chosen from the process window and confirmation wire bond analysis was carried out on the SiO/sub 2/ test vehicle. The same bond parameters were implemented on the low-k SiLK test vehicle, and were found to induce deformation of the low-k dielectric layer, resulting in the peeling of bond pad from the low-k dielectric. The wire bonded samples were subjected to ball shear and wire pull test. In the SiO/sub 2/ dielectric test vehicle, failure was always in the ductile Au ball during ball shear and at the neck during pull test. In the low-k SiLK test vehicle, the initial failures were bond pads tearing off the low-k dielectric. This paper discusses the bonding process optimization carried out in order to solve this issue and to achieve good bonding. This paper also reports the reliability of these devices under temperature cycle, high thermal storage and PCT (pressure cooker test) tests. Detailed failure analysis carried out on the bond pad failure is also reported.
{"title":"Wire bonding process impact on low-k dielectric material in damascene copper integrated circuits","authors":"V. Kripesh, M. Sivakumar, L. A. Lim, R. Kumar, M. Iyer","doi":"10.1109/ECTC.2002.1008203","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008203","url":null,"abstract":"This study investigates wire bonding impact on low-k dielectric material used in dual damascene copper integrated circuits. The paper focuses on wire bond process optimization required for devices with soft low-k dielectric material compared to device with hard standard silicon dioxide dielectric. A fine pitch (60 /spl mu/m bond pitch) wire bonding process was established on test vehicles with SiO/sub 2/ and low-k SiLK dielectrics. All wire bond process parameters were established on the SiO/sub 2/ test vehicle. The process optimization was carried out with emphasis on free air ball formation, first bond and wedge bond. Optimized process parameters were chosen from the process window and confirmation wire bond analysis was carried out on the SiO/sub 2/ test vehicle. The same bond parameters were implemented on the low-k SiLK test vehicle, and were found to induce deformation of the low-k dielectric layer, resulting in the peeling of bond pad from the low-k dielectric. The wire bonded samples were subjected to ball shear and wire pull test. In the SiO/sub 2/ dielectric test vehicle, failure was always in the ductile Au ball during ball shear and at the neck during pull test. In the low-k SiLK test vehicle, the initial failures were bond pads tearing off the low-k dielectric. This paper discusses the bonding process optimization carried out in order to solve this issue and to achieve good bonding. This paper also reports the reliability of these devices under temperature cycle, high thermal storage and PCT (pressure cooker test) tests. Detailed failure analysis carried out on the bond pad failure is also reported.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115249261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008165
E. Perfecto, L. Goldmann
Via stacking has been used successfully over the years during the fabrication of semiconductor personalization layers. This structure requires Chem-mech planarization to fabricate via studs and discrete wiring. In contrast, non planar structures result when sequential layers of metal and dielectric are deposited without the planarization step. During the fabrication of MCM-D, polyimide dielectric films are patterned to create a via opening, allowing for level-to-level connection. Traditionally, these vias are not stacked. In multilevel thin films, the more common via structures are either staircase or spiral. Even when the vias are co-centered, as is the case for power vias of some MCM-D products, the via diameter is increased from one level to the next level producing a reverse pyramid structure. IBM has developed stacked vias technology which simplifies and adds flexibility to the thin film design. This paper will discuss the processing aspects of stacked vias on a non-planar structure, and will present a mechanical finite element model for various via diameters (5, 10, 15, 20, and 25 um) on a four metal level structure. It will also contrast the effect on topography and planarity of stacked and non-stacked via structures.
{"title":"Increased thin film wiring density by stacked vias","authors":"E. Perfecto, L. Goldmann","doi":"10.1109/ECTC.2002.1008165","DOIUrl":"https://doi.org/10.1109/ECTC.2002.1008165","url":null,"abstract":"Via stacking has been used successfully over the years during the fabrication of semiconductor personalization layers. This structure requires Chem-mech planarization to fabricate via studs and discrete wiring. In contrast, non planar structures result when sequential layers of metal and dielectric are deposited without the planarization step. During the fabrication of MCM-D, polyimide dielectric films are patterned to create a via opening, allowing for level-to-level connection. Traditionally, these vias are not stacked. In multilevel thin films, the more common via structures are either staircase or spiral. Even when the vias are co-centered, as is the case for power vias of some MCM-D products, the via diameter is increased from one level to the next level producing a reverse pyramid structure. IBM has developed stacked vias technology which simplifies and adds flexibility to the thin film design. This paper will discuss the processing aspects of stacked vias on a non-planar structure, and will present a mechanical finite element model for various via diameters (5, 10, 15, 20, and 25 um) on a four metal level structure. It will also contrast the effect on topography and planarity of stacked and non-stacked via structures.","PeriodicalId":285713,"journal":{"name":"52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116534296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ECTC.2002.1008180
Young-Doo Jeon, S. Nieland, A. Ostmann, H. Reichl, K. Paik
Even though electroless Ni and Sn-Ag-Cu solder are widely used materials in electronic packaging applications, interfacial reactions of the ternary Ni-Cu-Sn system have not been known well because of their complexity. Because the growth of intermetallics at the interface affects reliability of solder joint, the intermetallics in Ni-Cu-Sn system should be identified, and their growth should be investigated. Therefore, in present study, interfacial reactions between electroless Ni UBM and 95.5Sn-4.0Ag-0.5Cu alloy were investigated focusing on morphology of the IMCs, thermodynamics, and growth kinetics.
尽管化学镀镍和Sn-Ag-Cu焊料是电子封装应用中广泛使用的材料，但由于其复杂性，三元Ni- cu - sn体系的界面反应尚未得到很好的了解。由于金属间化合物在界面处的生长会影响焊点的可靠性，因此需要识别Ni-Cu-Sn体系中的金属间化合物，并对其生长进行研究。因此，本研究主要研究了化学镀Ni - UBM与95.5Sn-4.0Ag-0.5Cu合金的界面反应，重点研究了IMCs的形貌、热力学和生长动力学。
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