Performance enhancement of single electron junction 1-bit full adder

I. Basith, Tareq Muhammad Supon, Ajit Muhury, R. Rashidzadeh, M. Ahmadi
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引用次数: 1

Abstract

The focus of this paper is to study the reliability issue of single-electron tunneling (SET) technology using multi-island structure for 1-bit full adder circuit. A new set of parameters are proposed in this paper showing better sensitivity towards the random background charge (RBC). Impact of temperature and background charge on the performance parameters and voltage swing are also analyzed. Multi-island clique (K-3) structure is implemented and compared with the designs reported in the literature.
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单电子结1位全加法器的性能增强
本文重点研究了采用多岛结构的1位全加法器电路的单电子隧穿技术的可靠性问题。本文提出了一组对随机背景电荷(RBC)有较好灵敏度的新参数。分析了温度和背景电荷对性能参数和电压摆幅的影响。实现了多岛团(K-3)结构,并与文献报道的设计进行了比较。
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