A 350-MHz combined TDC-DTC With 61 ps resolution for asynchronous ΔΣ ADC applications

Abstract

A combined Time-to-Digital Digital-to-Time Converter (TDC-DTC) is presented for use in a high-precision single-bit Asynchronous DeltaSigma ADC. It quantizes the 1-bit asynchronous square wave with 61 ps precision, obtaining a virtual sampling frequency of 16.4 GHz with only a 350 MHz clock. Measurements confirm that with this precision, the design of a single-bit Asynchronous DeltaSigma ADC obtaining 78 dB SNDR over a 500 kHz bandwidth is feasible using only a first-order noise shaping and with a limit cycle frequency of only 8 MHz. With this technique, both the order and the bandwidth requirements of the noise shaping filter can be relaxed, which significantly reduces the analog complexity of the DeltaSigma Modulator. The proposed architecture is therefore especially suited for low-voltage nanometer technologies.