{"title":"A Single-Controller-Four-Output Analog-Assisted Digital LDO with Adaptive-Time-Multiplexing Control in 65-nm CMOS","authors":"Yasu Lu, Feng Chen, P. Mok","doi":"10.1109/ESSCIRC.2019.8902511","DOIUrl":null,"url":null,"abstract":"This paper presents a single-controller-four-output analog-assisted digital LDO which can regulate four output voltage domains by sharing only one digital controller with an adaptive-time-multiplexing control scheme. The area of the digital controller is 62% smaller compared to the sum of the digital controller area of four independent LDOs. An analog-assisted loop and a push-pull auxiliary loop are used to take over the control in steady state to save quiescent power, reduce output ripple and enhance the response speed. A prototype is fabricated in a 65nm CMOS process. An undershoot voltage of 100mV is measured with a 47mA/20ns load step, resulting a figure-of-merit as low as 0.12ps.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2019.8902511","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
This paper presents a single-controller-four-output analog-assisted digital LDO which can regulate four output voltage domains by sharing only one digital controller with an adaptive-time-multiplexing control scheme. The area of the digital controller is 62% smaller compared to the sum of the digital controller area of four independent LDOs. An analog-assisted loop and a push-pull auxiliary loop are used to take over the control in steady state to save quiescent power, reduce output ripple and enhance the response speed. A prototype is fabricated in a 65nm CMOS process. An undershoot voltage of 100mV is measured with a 47mA/20ns load step, resulting a figure-of-merit as low as 0.12ps.