Case study of a high speed three-dimensional graphics chip set

Third Annual IEEE Proceedings on ASIC Seminar and Exhibit Pub Date : 1990-09-17 DOI:10.1109/ASIC.1990.186101

R. Eisenstadt

引用次数: 0

Abstract

Design efforts to implement a 3-D graphics chip set are presented. The set contains designs ranging from a 10000-gate 1.5-micron gate array to a 208-pin, 50000+-gate 1.0-micron silicon compiled design containing RAM and datapath structures. The resulting graphics system contains 85 ASIC chips representing 10 different designs. Overviews of design entry, logic synthesis, physical design, package selection, vector generation, simulation, and test program development are provided. Further information reflecting hardware requirements, and design cycle times is included.<>

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高速三维图形芯片的实例研究

介绍了实现三维图形芯片的设计方法。该组包含的设计范围从1万门1.5微米门阵列到208针，50000+门1.0微米硅编译设计，包含RAM和数据路径结构。由此产生的图形系统包含85个ASIC芯片，代表10种不同的设计。概述了设计入口，逻辑合成，物理设计，封装选择，矢量生成，仿真和测试程序的开发提供。还包括反映硬件要求和设计周期时间的进一步信息

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Third Annual IEEE Proceedings on ASIC Seminar and Exhibit

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