Self-Clamped P-shield SiC Trench IGBT for Low On-State Voltage and Switching Loss

Abstract

A novel self-clamped P-shield design in SiC trench-gate IGBT is proposed. An enhancement-mode (E-mode) PMOS and open-base PNP transistor are embedded at the emitter side by introducing an N-well into the P-shield region. In OFF -state, the P-shield is clamped at a low potential via the conduction of E-mode PMOS, maintaining a strong electric field shielding effect for trench gate oxide. In ON-state, the P-shield is floating electrically via the deep hole barrier formed by the N-well, enhancing the injection-enhancement (IE) effect. Under high collector-emitter voltage conditions, the P-shield is clamped via the punch-through of the open-base PNP transistor, effectively reducing saturation current. Furthermore, the self-clamped P-shield reduces the Miller capacitance and suppresses the negative gate capacitance during the switching transient, achieving low switching losses and high switching speed. As a result, the self-clamped P-shield SiC IGBT provides a new design solution to improving ON-, OFF -, and switching performance simultaneously.