SOG planarization for polysilicon and first metal interconnect in a one micron CMOS process

Abstract

The application of spin-on-glass (SOG) planarization at both the polysilicon and first metal level in a 1- mu m CMOS process developed for the manufacture of ASIC devices is described. At the polysilicon level, SOG planarization is considered for future applications since the planarization can be optimized for performance and reliability almost independently of the salicide module which is an integral part of the process. This is possible because SOG planarization is essentially a low-temperature process which does not result in degradation of the salicide. Its performance is compared to that achieved with BPSG planarization under first metal. Above first metal, SOG is used in the process for reasons of manufacturability. The performance is compared to that achieved using a previously developed resist etchback process. For both applications, SOG shows excellent performance, as illustrated by electrical data. The SOG deposition process is discussed along with relevant materials data.<>