A 10Gb/s active-inductor structure with peaking control in 90nm CMOS

Abstract

A PMOS-based active inductor circuit for high-speed I/O applications is presented. The active inductor can operate with low voltage headroom and requires no voltage boosting. A prototype output driver circuit using the active inductor is implemented in 90 nm CMOS. The peaking frequency and its corresponding gain magnitude of the active-inductor circuit can be adjusted to facilitate channel loss compensation. Operating at 10 Gb/s over a 6-in FR4 channel, as compared to the case when the active-inductor structure is disabled, the use of active inductor circuit in the transmitter side increases the vertical eye opening at the receiver side by a factor of two and reduces the peak-to-peak jitter of the received data by 30%. By keeping the current of the active inductor above a certain value, impedance variations are minimized and appropriate impedance matching is achieved (S22 less than -10 dB). The active-inductor circuit occupies 17 times 25 mum2 and has a low overhead power consumption of 0.8 mW, i.e., ~10% of the overall power of the prototype output driver.