A spreadsheet approach for early optimization of large bus switching performance

Abstract

A technique for optimizing bus performance early in the design cycle is described. The technique allows packaging-related aspects of bus delay to be analyzed in a spreadsheet format. The time required for receiver inputs to pass switching threshold is described as a series of simplex expression that can be entered into a spreadsheet for comparison of various design options. It assumes CMOS or TTL-like driver devices and unterminated receivers. Parameters that can be varied include driver output characteristics, receiver thresholds, number of receivers, bus partitioning, and card transmission line characteristics. An an example, analysis of design options for a large CMOS memory bus is demonstrated.<>