Low power FPGA-based implementation of decimating filters for multistandard receiver

Abstract

In this work a low power solution is provided for the implementation of decimation filter for multistandard wireless receiver. The reduced switching activity and low power dissipation are achieved through the reduction of the energy wasted by the clocking of storage units on every cycle. This technique known as the "clock gating" allows enabling the clock only when a load to a register is required. This also serves to "turn off" parts of the design by holding the clock steady during inactive periods. Analysis showed that by reducing switching activity in the overall system power consumption is reduced by about 23% compared to the same architecture where no clock gating is used