Performance and Yield Optimization of mm-Wave PLL Front-End in 65nm SOI CMOS

Abstract

A combination of LC-VCO and 2:1 CML static frequency divider has been fabricated in 65 nm SOI CMOS technology and operates at 70 GHz. A cascoded buffer amplifier is used in VCO-to-divider connection to compensate for the power losses caused by interconnect parasitics, and inductive peaking is employed for bandwidth enhancement. The bias condition of the frequency divider has been tuned to find an optimal bias point in existence of VCO and frequency divider operating range variation. The inter-die variation of VCO and divider performance variations over a wafer and their correlation have been estimated.