Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380848
Xuejin Wang, B. Bakkaloglu
Design of low drop-out (LDO) supply regulated 2.4 GHz low phase noise LC-tank voltage controlled oscillator (VCO) is presented. Low-frequency supply noise sensitivity of the VCO phase noise is derived, and output noise and power supply rejection (PSR) profile of the LDO is optimized for minimum supply pushing. The LDO PSR and output noise is optimized by shaping the LDO AC response and tuning the equivalent-series resistance (ESR) of the bypass capacitor, while achieving maximum LDO current efficiency. To verify the results, two 2.4 GHz LC-tank VCOs, with a PMOS and an NMOS switching pair respectively with associated PMOS supply regulators are designed and fabricated in a 0.18 mum, 7-layer metal CMOS process. The implemented VCOs achieve less than 95 dBc/Hz phase noise at 100 kHz offset with a current consumption of 2.2 mA. By utilizing the proposed regulator AC loop shaping, the VCO phase noise sensitivity to supply noise is improved by 30 dB for offset frequency up to 10 MHz with no phase noise peaking.
{"title":"A 2.4-GHz LC-Tank VCO with Minimum Supply Pushing Regulation Technique","authors":"Xuejin Wang, B. Bakkaloglu","doi":"10.1109/RFIC.2007.380848","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380848","url":null,"abstract":"Design of low drop-out (LDO) supply regulated 2.4 GHz low phase noise LC-tank voltage controlled oscillator (VCO) is presented. Low-frequency supply noise sensitivity of the VCO phase noise is derived, and output noise and power supply rejection (PSR) profile of the LDO is optimized for minimum supply pushing. The LDO PSR and output noise is optimized by shaping the LDO AC response and tuning the equivalent-series resistance (ESR) of the bypass capacitor, while achieving maximum LDO current efficiency. To verify the results, two 2.4 GHz LC-tank VCOs, with a PMOS and an NMOS switching pair respectively with associated PMOS supply regulators are designed and fabricated in a 0.18 mum, 7-layer metal CMOS process. The implemented VCOs achieve less than 95 dBc/Hz phase noise at 100 kHz offset with a current consumption of 2.2 mA. By utilizing the proposed regulator AC loop shaping, the VCO phase noise sensitivity to supply noise is improved by 30 dB for offset frequency up to 10 MHz with no phase noise peaking.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115009860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380993
Y. Yamaguchi, T. Kaho, K. Uehara
A highly integrated X-band frequency quadrupler MMIC using three-dimensional MMIC (3D-MMIC) technology is presented. It consists of four amplifiers, two doublers, and a 2-band elimination filter. These seven circuits are integrated on only a 2.25 mm times 1.05 mm chip. The third and fifth harmonic components, which are spurious components nearest to the desired component, are well suppressed. The desired/undesired ratio is about 40 dB. The MMIC supplies +5 dBm of the fourth harmonic component at input power as low as -10 dBm. The power dissipation of the MMIC is only 160 mW.
提出了一种采用三维MMIC (3D-MMIC)技术的高集成度x波段四倍频MMIC。它由四个放大器，两个倍频器和一个2波段消除滤波器组成。这七个电路集成在2.25 mm × 1.05 mm的芯片上。第三和第五谐波分量是最接近所需分量的杂散分量，它们被很好地抑制。理想/不理想的比值约为40分贝。MMIC在低至- 10dbm的输入功率下提供+ 5dbm的四次谐波分量。MMIC的功耗仅为160 mW。
{"title":"A Highly Integrated X-band Frequency Quadrupler MMIC using 3D-MMIC Technology","authors":"Y. Yamaguchi, T. Kaho, K. Uehara","doi":"10.1109/RFIC.2007.380993","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380993","url":null,"abstract":"A highly integrated X-band frequency quadrupler MMIC using three-dimensional MMIC (3D-MMIC) technology is presented. It consists of four amplifiers, two doublers, and a 2-band elimination filter. These seven circuits are integrated on only a 2.25 mm times 1.05 mm chip. The third and fifth harmonic components, which are spurious components nearest to the desired component, are well suppressed. The desired/undesired ratio is about 40 dB. The MMIC supplies +5 dBm of the fourth harmonic component at input power as low as -10 dBm. The power dissipation of the MMIC is only 160 mW.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121058854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380933
Pin-Cheng Huang, F. Chang, Shih-Fong Chao, Huei Wang
This paper presents a compact up-conversion mixer using commercial 0.18-μm CMOS technology for UWB system applications. To achieve broadband frequency response, low power consumption, and small chip size simultaneously, the folded structure and inductor-free matching network are adopted. The measured mixer demonstrates a measured wideband response from 1 to 11 GHz with a conversion loss of lower than 6 dB. The dc power consumption is 25 mW under a supply voltage of 1.8-V, with a compact chip size of 0.5 mm times 0.6 mm.
本文提出了一种紧凑的上变频混频器，采用商用0.18 μm CMOS技术，用于超宽带系统。为了同时实现宽带频响、低功耗和小芯片尺寸，采用了折叠结构和无电感匹配网络。测量的混频器显示了从1到11 GHz的测量宽带响应，转换损耗低于6 dB。在1.8 v供电电压下，直流功耗为25mw，芯片尺寸紧凑，为0.5 mm × 0.6 mm。
{"title":"A Miniature, Folded-Switching, Up-conversion Mixer for UWB Applications Using 0.18-μ CMOS Process","authors":"Pin-Cheng Huang, F. Chang, Shih-Fong Chao, Huei Wang","doi":"10.1109/RFIC.2007.380933","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380933","url":null,"abstract":"This paper presents a compact up-conversion mixer using commercial 0.18-μm CMOS technology for UWB system applications. To achieve broadband frequency response, low power consumption, and small chip size simultaneously, the folded structure and inductor-free matching network are adopted. The measured mixer demonstrates a measured wideband response from 1 to 11 GHz with a conversion loss of lower than 6 dB. The dc power consumption is 25 mW under a supply voltage of 1.8-V, with a compact chip size of 0.5 mm times 0.6 mm.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124798752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380915
M. Elmala, R. Bishop
An OFDM capable Doherty PA is implemented in 90 nm CMOS with integrated quadrature hybrid and impedance transformer. The two amplifiers are optimized to minimize AM-PM distortion. The PA achieves 25 dBm Psa, using 1.4 V supply with 24% PAE, and operates over 1 GHz of frequency range (from 4 GHz to 5 GHz). 3 dB to 6 dB back-off from P1dB is required to achieve -25 dB measured EVM across this band, making it suitable for WLAN and WiMAX applications. The measured AM-PM distortion varies from 4deg to 12.5deg across the 1 GHz range.
{"title":"A 90nm CMOS Doherty Power Amplifier with Integrated Hybrid Coupler and Impedance Transformer","authors":"M. Elmala, R. Bishop","doi":"10.1109/RFIC.2007.380915","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380915","url":null,"abstract":"An OFDM capable Doherty PA is implemented in 90 nm CMOS with integrated quadrature hybrid and impedance transformer. The two amplifiers are optimized to minimize AM-PM distortion. The PA achieves 25 dBm Psa, using 1.4 V supply with 24% PAE, and operates over 1 GHz of frequency range (from 4 GHz to 5 GHz). 3 dB to 6 dB back-off from P1dB is required to achieve -25 dB measured EVM across this band, making it suitable for WLAN and WiMAX applications. The measured AM-PM distortion varies from 4deg to 12.5deg across the 1 GHz range.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115027318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380923
J. Comeau, J. Cressler, M. Mitchell
This work investigates various design and layout optimization approaches for MOSFET-based series-shunt, single-pole double-throw (SPDT) switches in a commercially-available 130 nm silicon-germanium (SiGe) BiCMOS technology. The incorporation of deep-trench isolation, additional substrate contacts, and additional gate resistance for the series nMOS device are examined, and the impact of these design and layout optimizations on the switches insertion loss, bandwidth, isolation and linearity performance have been quantified across frequency. This experiment has yielded a SPDT switch with an insertion loss of - 1.4 dB, -1.5 dB, and -2.0 dB, at 5.8 GHz, 10 GHz, and 20 GHz, respectively, and an input-referred third-order intercept point (II P3) of 21 dBiu at 9.5 GHz, without the use of any process adders or additional supply voltages.
{"title":"Design and Layout Techniques for the Optimization of nMOS SPDT Series-Shunt Switches in a 130nm SiGe BiCMOS Technology","authors":"J. Comeau, J. Cressler, M. Mitchell","doi":"10.1109/RFIC.2007.380923","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380923","url":null,"abstract":"This work investigates various design and layout optimization approaches for MOSFET-based series-shunt, single-pole double-throw (SPDT) switches in a commercially-available 130 nm silicon-germanium (SiGe) BiCMOS technology. The incorporation of deep-trench isolation, additional substrate contacts, and additional gate resistance for the series nMOS device are examined, and the impact of these design and layout optimizations on the switches insertion loss, bandwidth, isolation and linearity performance have been quantified across frequency. This experiment has yielded a SPDT switch with an insertion loss of - 1.4 dB, -1.5 dB, and -2.0 dB, at 5.8 GHz, 10 GHz, and 20 GHz, respectively, and an input-referred third-order intercept point (II P3) of 21 dBiu at 9.5 GHz, without the use of any process adders or additional supply voltages.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116442881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380883
N. Tran, Bomson Lee, Jong-Wook Lee
We present the design of three key building blocks for UHF-band passive RFID tag chip, i.e., voltage multiplier, ASK demodulator, and internal clock generator. An analysis on a simple equivalent circuit of RFID tag chip for long reading range is presented taking into account the finite turn-on voltage of tag chip. The Schottky diodes used in the passive RFID tag chip were fabricated using titanium (Ti/Al/Ta/Al)-silicon (n-type) junction in 0.35 mum CMOS process, and the effect of size of Schottky diode on the turn-on voltage and the input impedance of the voltage multiplier was investigated. For 300 mV RF input voltage, the fabricated voltage multiplier using Schottky diodes generated output voltages of 1.5 V and corresponding voltage conversion efficiency of 45%. In addition, we propose an example circuit for internal oscillator of tag chip with digital calibration, which can generate precise copy of RFID reader timing signals.
我们提出了uhf频段无源RFID标签芯片的三个关键构建模块的设计，即电压乘法器，ASK解调器和内部时钟发生器。考虑到标签芯片的导通电压有限，对一种简单的RFID标签芯片等效电路进行了分析。采用0.35 μ m CMOS工艺，采用钛(Ti/Al/Ta/Al)-硅(n型)结制备了用于无源RFID标签芯片的肖特基二极管，并研究了肖特基二极管尺寸对电压乘数器导通电压和输入阻抗的影响。当射频输入电压为300 mV时，利用肖特基二极管制作的电压倍增器输出电压为1.5 V，相应的电压转换效率为45%。此外，我们还提出了一种带有数字校准的标签芯片内部振荡器示例电路，该电路可以精确地复制RFID阅读器的时序信号。
{"title":"Development of Long-Range UHF-band RFID Tag chip Using Schottky Diodes in Standard CMOS Technology","authors":"N. Tran, Bomson Lee, Jong-Wook Lee","doi":"10.1109/RFIC.2007.380883","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380883","url":null,"abstract":"We present the design of three key building blocks for UHF-band passive RFID tag chip, i.e., voltage multiplier, ASK demodulator, and internal clock generator. An analysis on a simple equivalent circuit of RFID tag chip for long reading range is presented taking into account the finite turn-on voltage of tag chip. The Schottky diodes used in the passive RFID tag chip were fabricated using titanium (Ti/Al/Ta/Al)-silicon (n-type) junction in 0.35 mum CMOS process, and the effect of size of Schottky diode on the turn-on voltage and the input impedance of the voltage multiplier was investigated. For 300 mV RF input voltage, the fabricated voltage multiplier using Schottky diodes generated output voltages of 1.5 V and corresponding voltage conversion efficiency of 45%. In addition, we propose an example circuit for internal oscillator of tag chip with digital calibration, which can generate precise copy of RFID reader timing signals.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128777687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380868
T. Tokairin, N. Matsuno, K. Numata, T. Maeda, S. Tanaka
This paper presents a new single PLL and single SSB-mixer architecture for a local signal generator of the Mode-1 MB-OFDM UWB systems. Using a VCO running at 8976 MHz and a divide-by-2 circuit, it can provide a 4488-MHz carrier signal with low-spurious levels, which is required to meet the spectrum mask requirements being considered in Japan and Europe. A divide-by-8.5/17 circuit using double-edge triggered operation is introduced to obtain 3432-and 3960-MHz carriers from the same VCO in order to save die area. This circuit generates 1056-and 528-MHz signals, and the required signals can be obtained by mixing these with 4488 MHz signal. The core area of the local signal generator fabricated in a 0.18-mum CMOS technology is 0.67 mm2. The spurious levels for the 4488-MHz carrier are below -41 dBc.
{"title":"A 0.18-/spl mu/m CMOS Low-spurious Local Signal Generator for MB-OFDM UWB Radio","authors":"T. Tokairin, N. Matsuno, K. Numata, T. Maeda, S. Tanaka","doi":"10.1109/RFIC.2007.380868","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380868","url":null,"abstract":"This paper presents a new single PLL and single SSB-mixer architecture for a local signal generator of the Mode-1 MB-OFDM UWB systems. Using a VCO running at 8976 MHz and a divide-by-2 circuit, it can provide a 4488-MHz carrier signal with low-spurious levels, which is required to meet the spectrum mask requirements being considered in Japan and Europe. A divide-by-8.5/17 circuit using double-edge triggered operation is introduced to obtain 3432-and 3960-MHz carriers from the same VCO in order to save die area. This circuit generates 1056-and 528-MHz signals, and the required signals can be obtained by mixing these with 4488 MHz signal. The core area of the local signal generator fabricated in a 0.18-mum CMOS technology is 0.67 mm2. The spurious levels for the 4488-MHz carrier are below -41 dBc.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124641206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380882
Jong-Eun Jang, Hoon Lee, Seung-Wan Choi, K. Ahn, Myoung-Sub Jung, Eui-Seok Song, Juno Kim, Hyoung-Hwan Ron, Gi-Beom Kim, Sung-Woo Bae, Ha-Ryoung Oh, Y. Seong, Jun-Seok Park
A fully integrated 900-MHz direct-conversion transceiver for mobile RFID system is presented. The transceiver consists of a low noise amplifier, a down-conversion mixer, a band pass filter, and programmable gain amplifier (PGA) for RX path; and a power amplifier, an up-conversion mixer, a low-pass filter, and a PGA for TX path. In addition, the fractional N PLL is integrated to cover different frequency standards for different nations. The transceiver meets the dense reader environment specifications.
{"title":"A 900-MHz Direct-Conversion Transceiver for Mobile RFID Systems","authors":"Jong-Eun Jang, Hoon Lee, Seung-Wan Choi, K. Ahn, Myoung-Sub Jung, Eui-Seok Song, Juno Kim, Hyoung-Hwan Ron, Gi-Beom Kim, Sung-Woo Bae, Ha-Ryoung Oh, Y. Seong, Jun-Seok Park","doi":"10.1109/RFIC.2007.380882","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380882","url":null,"abstract":"A fully integrated 900-MHz direct-conversion transceiver for mobile RFID system is presented. The transceiver consists of a low noise amplifier, a down-conversion mixer, a band pass filter, and programmable gain amplifier (PGA) for RX path; and a power amplifier, an up-conversion mixer, a low-pass filter, and a PGA for TX path. In addition, the fractional N PLL is integrated to cover different frequency standards for different nations. The transceiver meets the dense reader environment specifications.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121339514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380853
M. Hartmann, C. Wagner, K. Seemann, J. Platz, H. Jager, R. Weigel
This paper presents a single chip receiver front-end, including low-noise amplifier and mixer, for application in automotive radar systems at 77 GHz. The circuit has been implemented in a SiGe HBT technology. The complete circuit occupies 1030 times 1130 mum2 including bond pads and dissipates 440 mW from a 5.5 V supply. The front-end shows a minimum measured single sideband noise figure (SSB NF) of 11.5 dB and a maximum conversion gain of 30 dB at 77 GHz. Linearity measurements show a 1 dB input compression point of -26 dBm and a third order intercept point of -21.6 dBm at 77 GHz.
{"title":"A Low-Power Low-Noise Single-Chip Receiver Front-End for Automotive Radar at 77 GHz in Silicon-Germanium Bipolar Technology","authors":"M. Hartmann, C. Wagner, K. Seemann, J. Platz, H. Jager, R. Weigel","doi":"10.1109/RFIC.2007.380853","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380853","url":null,"abstract":"This paper presents a single chip receiver front-end, including low-noise amplifier and mixer, for application in automotive radar systems at 77 GHz. The circuit has been implemented in a SiGe HBT technology. The complete circuit occupies 1030 times 1130 mum2 including bond pads and dissipates 440 mW from a 5.5 V supply. The front-end shows a minimum measured single sideband noise figure (SSB NF) of 11.5 dB and a maximum conversion gain of 30 dB at 77 GHz. Linearity measurements show a 1 dB input compression point of -26 dBm and a third order intercept point of -21.6 dBm at 77 GHz.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114742990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380972
E. Klumperink, Qiaohui Zhang, G. Wienk, R. Witvers, J. B. D. Vaate, B. Woestenburg, B. Nauta
A 0.18 mum CMOS low noise amplifier (LNA) achieves sub-1 dB noise figure over more than an octave of bandwidth without external noise matching components. It is designed for a future radio telescope, requiring millions of cheap LNAs mounted directly on phased array antenna elements. The short distance between antenna and LNA and low frequency below 2 GHz allows for using an LNA with reflective input impedance, increasing the gain with 6 dB. Without any matching network, very low noise figure is achieved over a wide bandwidth. At 90 mW power, sub-1 dB Noise is achieved for 50 Omega source impedance over a 0.8-1.8 GHz band without external coils, and S21>20 dB, OIP2>25 dBm and OIP3>15 dBm. Preliminary results with 150 Omega source impedance show noise temperatures as low as 25 K around 900 MHz.
{"title":"Achieving Wideband sub-1dB Noise Figure and High Gain with MOSFETs if Input Power Matching is not Required","authors":"E. Klumperink, Qiaohui Zhang, G. Wienk, R. Witvers, J. B. D. Vaate, B. Woestenburg, B. Nauta","doi":"10.1109/RFIC.2007.380972","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380972","url":null,"abstract":"A 0.18 mum CMOS low noise amplifier (LNA) achieves sub-1 dB noise figure over more than an octave of bandwidth without external noise matching components. It is designed for a future radio telescope, requiring millions of cheap LNAs mounted directly on phased array antenna elements. The short distance between antenna and LNA and low frequency below 2 GHz allows for using an LNA with reflective input impedance, increasing the gain with 6 dB. Without any matching network, very low noise figure is achieved over a wide bandwidth. At 90 mW power, sub-1 dB Noise is achieved for 50 Omega source impedance over a 0.8-1.8 GHz band without external coils, and S21>20 dB, OIP2>25 dBm and OIP3>15 dBm. Preliminary results with 150 Omega source impedance show noise temperatures as low as 25 K around 900 MHz.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114783111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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