Skillfully diminishing antenna effect in layer assignment stage

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test Pub Date : 2014-04-28 DOI:10.1109/VLSI-DAT.2014.6834859

Chih-Chien Lin, Wen-Hao Liu, Yih-Lang Li

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引用次数: 1

Abstract

Antenna effect is an important issue that critically impacts the reliability and yield of integrated circuits. The dynamic-programming-based (DP-based) layer assignment method has been adopted to minimize antenna violation by enumerating all possible solutions and pruning inferior solutions. However, the complexities of modern circuits have significantly increased, likely causing the DP-based method to consume much more runtime and memory space. In this paper, we propose a skillful method to effectively Diminish Antenna effect in Layer Assignment Stage (DALAS). Unlike previous work that needs to search for separator locations and thus requires exploring much more solution space, DALAS does not need to search for separator locations and can deal with local and global antenna effects while trying to keep total via count and total overflow minimal. Experiment results show that DALAS is the first work to expel all antenna violations with similar via count to that produced by previous works [3][5] for the benchmarks in ISPD'08 Global Routing Contest.

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在分层阶段巧妙地减小天线效应

天线效应是影响集成电路可靠性和成品率的一个重要问题。采用基于动态规划(dp)的分层分配方法，通过列举所有可能解并剔除劣解，使天线冲突最小化。然而，现代电路的复杂性已经显著增加，可能导致基于dp的方法消耗更多的运行时和内存空间。在本文中，我们提出了一种巧妙的方法来有效地消除层分配阶段(DALAS)中的天线效应。不像以前的工作需要搜索分离器位置，因此需要探索更多的解决方案空间，DALAS不需要搜索分离器位置，可以处理局部和全局天线效应，同时尽量保持总通过数和总溢出最小。实验结果表明，在ISPD’08全球路由竞赛的基准测试中，DALAS是第一个排除所有通过数与先前工作[3][5]相似的天线违规的工作。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test

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