M. Voelkel, M. Dietz, R. Weigel, A. Hagelauer, D. Kissinger
{"title":"A low-power 60-GHz integrated sixport receiver front-end in a 130-nm BiCMOS technology","authors":"M. Voelkel, M. Dietz, R. Weigel, A. Hagelauer, D. Kissinger","doi":"10.23919/EUMIC.2017.8230663","DOIUrl":null,"url":null,"abstract":"In this paper a 60 GHz monolithic low-power sixport receiver front-end for high precision industrial radar systems is presented. The measurement principle is based on the passive superposition and power detection of two incident millimeter-wave signals. The integrated receiver has been designed using a 0.13 μm SiGe BiCMOS process from IHP (SG13G2) and includes a low noise amplifier (LNA), the passive sixport structure and four detectors. The signal processing in the baseband is done with an ADC-board designed with components from Texas Instruments and a Cyclone IV FPGA board. The integrated receiver circuit has a size of 1320 pm × 950 pm and a low power consumption of 73 mW from a 3.3 V power supply.","PeriodicalId":120932,"journal":{"name":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 12th European Microwave Integrated Circuits Conference (EuMIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/EUMIC.2017.8230663","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
In this paper a 60 GHz monolithic low-power sixport receiver front-end for high precision industrial radar systems is presented. The measurement principle is based on the passive superposition and power detection of two incident millimeter-wave signals. The integrated receiver has been designed using a 0.13 μm SiGe BiCMOS process from IHP (SG13G2) and includes a low noise amplifier (LNA), the passive sixport structure and four detectors. The signal processing in the baseband is done with an ADC-board designed with components from Texas Instruments and a Cyclone IV FPGA board. The integrated receiver circuit has a size of 1320 pm × 950 pm and a low power consumption of 73 mW from a 3.3 V power supply.
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