Observability Driven Path Generation for Delay Test Coverage Improvement in Scan Limited Circuits

Abstract

Delay test is used to verify the timing performance of integrated circuits. The test requires launching rising or falling transitions into the circuit and capturing the results after the specified delay. All the sequential elements in the design are required to be implemented with scan flip-flops such that the captured data can be observed for correct behavior. If the result is captured at a non-scan flip-flop, or a memory, it cannot be read out, resulting in fault coverage loss. This research describes an observability-based algorithm to transfer results captured in non-scan flip-flops to scan flip-flops using low speed functional clock cycles, termed coda cycles, so the results can be read out. We demonstrate the algorithm using path delay test on ISCAS89 benchmark circuits, where a fraction of the scan flip-flops have been made non-scan, and demonstrate the improvement in coverage when adding coda cycles to the clocking method.