{"title":"Design and implementation of an 11-bit non-linear interpolation DAC","authors":"S. Eisa, K. Shehata, H. Ragai","doi":"10.1080/00207210701827855","DOIUrl":null,"url":null,"abstract":"In this paper a novel design of an 11 bit digital-to-analog converter (DAC) is introduced. The design is to be integrated in a direct digital frequency synthesizer (DDKS). The designing of a DAC is critical due to its poor performance and low speed. The proposed design consists of three modules, a linear DAC, a nonlinear DAC and a nonlinear interpolation DAC. Each module contributes in enhancing the DAC performance. The DAC is integrated and simulated using Mentor Graphic tools. The simulation was done using a 3.3V, 0.35mu CMOS technology","PeriodicalId":399250,"journal":{"name":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","volume":"&NA; 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1080/00207210701827855","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
In this paper a novel design of an 11 bit digital-to-analog converter (DAC) is introduced. The design is to be integrated in a direct digital frequency synthesizer (DDKS). The designing of a DAC is critical due to its poor performance and low speed. The proposed design consists of three modules, a linear DAC, a nonlinear DAC and a nonlinear interpolation DAC. Each module contributes in enhancing the DAC performance. The DAC is integrated and simulated using Mentor Graphic tools. The simulation was done using a 3.3V, 0.35mu CMOS technology
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