Ultra-thin Ta/sub 2/O/sub 5/SiO/sub 2/ gate insulator with TiN gate technology for 0.1/spl mu/m MOSFETs

Abstract

We have developed a new Ta205/Si02 gate insulator with a TIN gate electrode technology to break through the limitation of a thin SiOz gate insulator with a poly-Si electrode. We successfully fabricated nMOSFETs with stable operation and high drive current for the first time. Ultra thin chemically oxidized SiOz (less than 2 nm) combined with Ta205 provides a stable interface which improves Gm and reliability of transistor. High drive current (Idmax = 0.74 mA/pm at Vg = Vd = 3.0V) and good sub-threshold slope (S-factor = 76 mV/dec.) were obtained with Teq of 2.8nm and gate length of 0.35 Hm nMOSFETs. Introduction Deep sub-micron devices of less than 0.1 pm encounter a scaling limit of the Si02 gate insulator because of its high leakage current due to direct tunneling effects. The gate depletion effect is also serious issue for such devices. In order to break through these problems, we have to develop a new high Er gate insulator material having thick physical thickness and metal-gate technology. TazO5 (Er = 25 in bulk) and TiN are most promising candidates for future gate insulator and gate electrode materials respectively'). Though intensive investigations about Ta205 have been done for storage capacitors in future G-bit scale DRAMsZ4), there are no reports on Ta205 used for gate insulator for deep sub-micron devices. In view of mobility and reliability, we have developed Ta205/Si02 system for gate insulator with an equivalent Si02 thickness of less than 5 nm and TIN gate technology, and fabricated 0.35 pm nMOSFETs. One concern with the use of Si02 as an interlayer is its thickness and controllability. Since an insulator film thickness of less than 3 nm is required for 0.1 pm transistors, the SiOz interlayer should be very thin (less than 2 nm) so as not to suppress the advantage of utilizing high Er material. We have grown an ultra thin S O z interlayer by HNO, boiling and Nz annealing at temperatures of 700°C or 800°C for 30 min. Fabrication Process Figure 1 shows a process flow and schematic cross section of a Taz05/Si02 gate insulator nMOSFET. Following the conventional LOCOS isolation, the Si active region was oxidized by various methods as listed in Table 1 . Si02 thicknesses are calculated from Si 2p X P S spectra. We also prepared the non-oxidation sample by dipping HF solution before the TazO5 CVD as a control. TazO5 films were deposited by LPCVD at 410°C using Ta(OC2H5)5 and O2 gases. These films were annealed in O2 ambient at 800°C for 60 sec TIN was sputtered on Ta205 films as the gate electrode. After the gate definition, the source and drain were formed by ion implantation of As' to fabricate single-drain nMOSFETs. Impurity activation was done by RTA at 800°C for 60 sec. Other process and device parameters are also listed in Table 1. Teq are calculated from capacitance data under the accumulation condition using large MOS diodes Results and Discussion Figure 2 and Figure 3 show typical I-V and sub-threshold characteristics for a sample #2A with Lg of 0.35 pm and Teq of 2.8 nm. Excellent drive current of 0.74 mA/pm (Vg = Vd = 3.0V) and very sharp sub-threshold slope of 76 mvldecade are achieved. Source/drain resistance extracted from these devices is about 500 . Q pm. Gate, sourcddrain, and substrate leakage current of sample #2 nMOSFET are plotted in Figure 4. The leakage current in our devices are the same level as those of pure-SiOz5). Figure 5 shows the transconductance dependence of equivalent oxide field (Eeq). Gm of the TazOS/SiOz sample (#l, #3) is improved significantly compared with the non-oxidation sample (#4). This suggests that carrier scattering due to interface states is effectively suppressed with a interlayer SOz. Reliability is also key issue for gate insulator. Vth shift with electron injection stress were examined for each sample. Figure 6 shows the Vth shift (AVth) for electron injection. Electrons were injected from the inversion layer b applying a positive gate voltage more than 0.25V is observed in sample #4 after 1.0 C/cmZ electron injection. This corresponds to more than 8.le-8 C/cm2 negative charges (electrons) trapped at the interface, if we assume all electrons are trapped at the Ta205/Si interface. For the Taz05/SiOZ system, on the contrary, AVth is very small. In sample #1, Gm is slightly degraded by electron injection for Vg ranging from Vth to 2V with increased electron injection as shown in Figure 7, but above that voltage its values are recovered. These differences of electrical properties by annealing temperatures are thought to be related to the quality of interlayer SiOz and/or interface. As shown in Figure 8, the Si02 peak of sample #2 shift to higher binding energy support these results. Another negative phenomenon is observed in non-oxidation sample (M). After the electron injection, it has a hysteresis property as depicted in Figure 9. It is thought that due to the large amount of interface trap generation, the electric field from the gate electrode is shielded by them and it impairs gate controllability. The above results indicate that ultra thin (less than 2 nm) interlayer Si02 play a very important role for Ta205/SiOz gate insulator transistor operation for improving Gm and reliability. Figure 10 shows ratio of gate channel capacitance to accumulation gate capacitance as a function of equivalent oxide thickness with the case of phosphorus doped poly-Si gate electrode. Though gate channel capacitance have not reached the maximum value due to the finite inversion layer thickness, the ratios are improved compare with poly-Si gate. This indicates an advantage of the metal-gate technology for future deep sub-micron devices Conclusion In this paper, we demonstrated the TazOs/Si02 gate insulator and TiN gate electrode nMOSFETs for the first time. We realized the high drive current (Idmax = 0.74 mA/pm at Vg = Vd = 3.0V at Teq = 2.8nm and Lg = 0.35 pm) and good sub-threshold slope (S-factor = 76 mV/dec.). We also reported that the high quality ultra thin chemically oxidized Si02 (annealed up to 800°C in N2) placed at the Ta205/Si-interface provides a stable interface with larger Gm and high reliability. Consequently, we showed that a Ta2O5/SiO2 gate insulator with TIN gate electrode system broke through the limitation of conventional Si02 gate insulator with a poly-Si electrode. with injection level of 0.01 N c m Y . A drastic positive Vth shift of References [l] T. Ohmi, Jpn. J. Appl. Phys., vol33 (1994), p 6747. [2] S. Kamiyama et al., J. Electrochem. SOC, vol. 140 (1993), p.1617. [3] Y. Takaishi et al., IEDM Tech. Dig (1994), p 839. [4] T. Kaga et al., IEDM Tech. Dig. (1994), p.927 [SI K F.Schuegraf et al., IEDM Tech. Dig (1994), p.609. 135 4-93081 3-75-1 I97 1997 Symposium on VLSl Technology Digest of Technical Papers