High performance sub-tenth micron CMOS using advanced boron doping and WSi/sub 2/ dual gate process

Abstract

High performance sub-tenth micron CMOS, exhibiting a record ring oscillator delay of 13.6 ps at 1.5 V, has been fabricated. Solid-phase diffusion from BSG was successfully utilized in CMOS fabrication for shallow p/sup +/ junction formation. To eliminate reverse short channel effect and improve punch-through immunity of nMOS, a 'channel implantation after source/drain activation' method was used. Combining these techniques, high speed CMOS operation at 0.07 /spl mu/m with acceptable stand-by leakage was obtained. WSi/sub 2//poly dual gate process without extra mask steps is also demonstrated.