Low Power Spiking Neural Network Circuit with Compact Synapse and Neuron Cells

Abstract

Spiking neural networks performs efficient learning and recognition tasks by mimicking the neural biology of human brain. To realize a large-scale network on chip for mobile applications an area and power optimized electronic neuron along with synapse is essential. In this paper we present an analog CMOS based implementation of neuron and synapse circuits realized using 180nm process. The neurons integrate input currents from the synapse inputs and generate a spike output event based on the membrane potential. The proposed circuits have been optimized for area and power consumption and therefore can be used as key components to form a large spiking neural network.