On Handling Memory Scan Chains

Abstract

Memories from the Library vendor come as a hard macro in the design. With the increased focus on meeting timing requirements, memories are provided in an integrated form from vendor. These integrated memory hard macros not only consist of SRAM read-write behavior but also comprise of scan chains and bypass logic around SRAM. This bypass logic consists of shadow cells which are already stitched into small scan chains inside the hard macro. Since this whole memory bypass and shadow logic is inside hard macro, it can be treated as a separate timing closed module in the design. Because of the separate timing closure process, there can be an occurrence of timing violation during silicon test on the logic interface between the SoC and the hard macro. There is a need to have an optional mode where designer should have freedom to generate the patterns with or without consideration of the capture mode of the memory scan cells. In this paper, we present a methodology to handle memory scan chains by controlling the memory clock during capture, using a combination of control signals which already exist in the design.