iSPLICE3: a new simulator for mixed analog/digital circuits

1989 Proceedings of the IEEE Custom Integrated Circuits Conference Pub Date : 1989-05-15 DOI:10.1109/CICC.1989.56745

E. L. Acuna, J. Dervenis, A. J. Pagones, R. Saleh

引用次数: 12

Abstract

A simulator called iSPLICE3 is described for the analysis of mixed analog/digital circuits is described. It combines electrical, switch-level timing and logic simulation modes using event-driven selective-trace techniques. This simulator features a hierarchical schematic capture package called iSPI for design entry and simulation control. It uses a novel approach to improve the speed and robustness of the DC solution. The details of the simulator architecture, circuit partitioning, mixed-mode interface, and event scheduling are provided along with the results of mixed-mode simulations of a recently designed memory circuit

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iSPLICE3:用于混合模拟/数字电路的新型模拟器

描述了用于分析混合模拟/数字电路的模拟器iSPLICE3。它结合了电气，开关级时序和逻辑仿真模式，使用事件驱动的选择性跟踪技术。该模拟器具有一个称为iSPI的分层原理图捕获包，用于设计入口和仿真控制。它采用了一种新颖的方法来提高直流解决方案的速度和鲁棒性。本文提供了模拟器的结构、电路划分、混合模式接口和事件调度的细节，以及最近设计的存储电路的混合模式仿真结果

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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1989 Proceedings of the IEEE Custom Integrated Circuits Conference

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