On-chip interconnect modeling technologies

Abstract

Summary form only given. On-chip interconnect must be accounted for at all levels of the design hierarchy, starting with synthesis, through physical design and ending with verification. Each level of the design hierarchy brings its unique challenge to interconnect modeling. Decisions made at the synthesis level have the greatest influence on the final interconnect design, yet one must deal with the uncertainty of having no physical design at this stage. During physical design, the uncertainty gradually decreases as the layout takes shape while the accuracy requirements on the interconnect models become more demanding. At the post-layout verification stage, there are no physical uncertainties. However for final verification, the fact that interconnect plays a dominant role in all performance parameters of the design, i.e., power, system delay, area and signal integrity, necessitates the use of extremely accurate interconnect models. This paper focuses on on-chip interconnect modeling technologies for post-layout verification (often called "parasitic extraction") and characterization/silicon-correlation which is essential to interconnect modeling at all levels. The state-of-the-art in "parasitic extraction" is reviewed and strengths and shortcomings are discussed. The need for establishing correlation with silicon is emphasized. Various popular measures of accuracy are scrutinized and the concept of accuracy in performance variables is introduced. Finally, the impact of interconnect modeling error on performance and signal integrity verification is discussed.