Analyzing Fault Tolerance Behaviour in Memristor-based Crossbar for Neuromorphic Applications

Abstract

One major operation in neuromorphic computing is vector-matrix multiplication (VMM), which is required during training and inference phases, and is expensive in terms of power consumption and latency. Hardware accelerators using emerging technologies like memristor crossbars can be used to speed up the process. Various faults in the crossbar can introduce errors in VMM computation. Existing methods to handle faults using retraining and remapping incur overheads in terms of hardware, power and delay. In this paper the impact of faults on memristor-based crossbars are explored to analyze the overall accuracy of VMM operations. It has been observed that in presence of limited number of faults, the accuracy is not significantly affected. However, as the number of faults increases, the error in computation also increases. The proposed approach works in two phases, high-level fault detection and low-level fault detection. In the first phase, the percentage of stuck-at faults in the crossbar is identified, and if it lies below a threshold the second phase is skipped. In the second phase, an efficient method to identify the exact location of the faults is used. The approach required less number of read/write operations as compared to existing works in the literature.