Improving bandwidth and error rate in flash converters

Abstract

To achieve high input bandwidth, the flash architecture of Figure 1 vas used. A preamp buffers each of the 257 latching comparators improving dynamic response and isolating the input and reference ladder from snitching transients. Dual supplies (+SV and -5.2V) are used to provide a convenient ground centered input span with large over-range capability. The extra headroom afforded by dual supplies permits a large rwerse bias on the collector-base junctions of the input transistors. This avoids the distortion caused by voltage dependent input capacitance found in single supply flash ADCs.[l] A special form of cascode reduces Miller capacitance loading of the input pair wbile maintaining high switching speed. The small physical siie of the input devices (5.5 x 1.0 um emitters) leads to a tiny input capacitance of ZOpF, and contributes to high input bandwidth.