Evolution of CMOS Technology at 32 nm and Beyond

Abstract

Over the last 15 years, there has been a new CMOS technology node approximately every two years. The key feature of every node has been 2X density shrink and ~35% performance gain per technology node. Chip power has been increasing rapidly, approaching air cool limit. Power limit is transforming CMOS scaling to more of a density driver. As we move to 32 nm node and beyond a number of additional fundamental challenges are faced, which may force additional rethinking of how scaling has been done. This paper is an overview of some upcoming challenges and possible ways of addressing them.