{"title":"Low-voltage indoor energy harvesting using photovoltaic cell","authors":"Hong-Yi Huang, Shao-Zu Yen, Jhen-Hong Chen, Hao-Chiao Hong, Kuo-Hsing Cheng","doi":"10.1109/DDECS.2016.7482472","DOIUrl":null,"url":null,"abstract":"This work presents a low-voltage indoor energy harvesting using photovoltaic cell. The system doesn't use a dc-dc converter to boost the output voltage so that large external inductors and large capacitors are eliminated. A rechargeable battery is connected to the output for storing the energy. No other external components are needed in the system. A test chip is implemented using a 0.18um CMOS process with a chip area of 0.85×0.85mm2 and a power consumption of 272uW. This solar cell provides a voltage of 0.4V~0.55V to the test chip at a minimum illumination of 61~625 Lux. A maximum efficiency of 54% can be obtained when the supply voltage is 0.5V.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DDECS.2016.7482472","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
This work presents a low-voltage indoor energy harvesting using photovoltaic cell. The system doesn't use a dc-dc converter to boost the output voltage so that large external inductors and large capacitors are eliminated. A rechargeable battery is connected to the output for storing the energy. No other external components are needed in the system. A test chip is implemented using a 0.18um CMOS process with a chip area of 0.85×0.85mm2 and a power consumption of 272uW. This solar cell provides a voltage of 0.4V~0.55V to the test chip at a minimum illumination of 61~625 Lux. A maximum efficiency of 54% can be obtained when the supply voltage is 0.5V.