This work presents a fifth-order OTA-C band-pass filter applying Elliptic low-pass filter and complex filter techniques. The frequency error of the filter due to the effect of process variations is induced by integrating the passive components with the operational transconductance amplifier on chip. A filter circuit with automatic calibration scheme can make the frequency less dependent on process, voltage, and temperature variations. The layout of a test chip is realized using a 0.18 um 1P6M CMOS process. Post-layout simulation demonstrates that the center frequency of the band pass filter is 450 kHz and the dynamic range is 35 dB, It has a total power consumption of 0.14mW.
{"title":"Gm-C filter with automatic calibration scheme","authors":"Hong-Yi Huang, Kun-Yuan Chen, Jia-Hao Xie, Ming-Ta Lee, Hao-Chiao Hong, Kuo-Hsing Cheng","doi":"10.1109/DDECS.2016.7482471","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482471","url":null,"abstract":"This work presents a fifth-order OTA-C band-pass filter applying Elliptic low-pass filter and complex filter techniques. The frequency error of the filter due to the effect of process variations is induced by integrating the passive components with the operational transconductance amplifier on chip. A filter circuit with automatic calibration scheme can make the frequency less dependent on process, voltage, and temperature variations. The layout of a test chip is realized using a 0.18 um 1P6M CMOS process. Post-layout simulation demonstrates that the center frequency of the band pass filter is 450 kHz and the dynamic range is 35 dB, It has a total power consumption of 0.14mW.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117218145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-20DOI: 10.1109/DDECS.2016.7482453
A. Nocua, A. Virazel, A. Bosio, P. Girard, C. Chevalier
Power management techniques are applied at high abstraction levels to reduce chip power consumption. Accurate and efficient power models are needed as early as possible in the design flow to ensure that correct saving decisions are taken. However, accuracy at those levels cannot be ensured, as there is not exact knowledge of the circuit structure. Then, power models based on estimation techniques at lower abstraction levels are desired. In this work, we propose a hybrid power modeling approach based on an effective library characterization methodology and an efficient power estimation flow to accurately assess gate-level power consumption. The main idea is to enhance the high-level power models by providing realistic information of the physical design. We perform experiments on ISCAS'85 benchmark circuits synthesized with a 28nm FDSOI technology. To prove the validity of our approach, we compare our results with SPECTRE simulations and show that we can achieve a 144X speedup on the runtime with a transistor-like accuracy.
{"title":"A hybrid power modeling approach to enhance high-level power models","authors":"A. Nocua, A. Virazel, A. Bosio, P. Girard, C. Chevalier","doi":"10.1109/DDECS.2016.7482453","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482453","url":null,"abstract":"Power management techniques are applied at high abstraction levels to reduce chip power consumption. Accurate and efficient power models are needed as early as possible in the design flow to ensure that correct saving decisions are taken. However, accuracy at those levels cannot be ensured, as there is not exact knowledge of the circuit structure. Then, power models based on estimation techniques at lower abstraction levels are desired. In this work, we propose a hybrid power modeling approach based on an effective library characterization methodology and an efficient power estimation flow to accurately assess gate-level power consumption. The main idea is to enhance the high-level power models by providing realistic information of the physical design. We perform experiments on ISCAS'85 benchmark circuits synthesized with a 28nm FDSOI technology. To prove the validity of our approach, we compare our results with SPECTRE simulations and show that we can achieve a 144X speedup on the runtime with a transistor-like accuracy.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125167690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-20DOI: 10.1109/DDECS.2016.7482455
Dmitry Osipov, S. Paul
This paper presents an 8 channel neural stimulator ASIC for biphasic stimulation of the visual cortex, realized in a 0.35 μm AMS HV process. Each channel is composed of an SPI interface, an 8-bit current digital-to-analog converter (DAC) and 120 V compliant HV output stage. Thus it is possible to deliver to the tissue arbitrary current waveforms with amplitudes up to ±10.24 mA with 40 μA steps. According to the simulation results the maximum differential non-linearity is equal to 0.27 LSB. The on board current reference provides the output current of 16 μA with the variation of 90 ppm/°C in the temperature range of 0-85° C. While the anodic and cathodic currents mismatch does not exceed 13 μA. The HV output interface of the ASIC was previously fabricated and measured. The measured interpulse leakage current does not exceed 60 pA.
{"title":"8 Channel neural stimulation ASIC for epidural visual cortex stimulation with on board 90 ppm/°C current reference","authors":"Dmitry Osipov, S. Paul","doi":"10.1109/DDECS.2016.7482455","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482455","url":null,"abstract":"This paper presents an 8 channel neural stimulator ASIC for biphasic stimulation of the visual cortex, realized in a 0.35 μm AMS HV process. Each channel is composed of an SPI interface, an 8-bit current digital-to-analog converter (DAC) and 120 V compliant HV output stage. Thus it is possible to deliver to the tissue arbitrary current waveforms with amplitudes up to ±10.24 mA with 40 μA steps. According to the simulation results the maximum differential non-linearity is equal to 0.27 LSB. The on board current reference provides the output current of 16 μA with the variation of 90 ppm/°C in the temperature range of 0-85° C. While the anodic and cathodic currents mismatch does not exceed 13 μA. The HV output interface of the ASIC was previously fabricated and measured. The measured interpulse leakage current does not exceed 60 pA.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127927048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-20DOI: 10.1109/DDECS.2016.7482454
O. Novák, Jiri Jenícek, M. Rozkovec
Usually, test pattern decompressors with dynamic reseeding are reset before starting a new test pattern decoding. The first few scan chain slices are then filled with test vectors that have lower decodability as the number of free variables is limited by the test access mechanism bandwidth. We have found that it is possible to increase the number of free variables in the equations describing the care bits encoding by fast creating and wide spreading as many as possible independent linear combinations of the tester bits and using them for the scan chain loading. We propose a decompressor combining a combinational linear decompressor and an LFSR like automaton that effectively distributes the free variables within the test pattern. The proposed test pattern decompressor outperforms the de-codability of other decompressors with similar hardware overhead and it reduces the test time due to a possible reduction of the decompressor preloading.
{"title":"Sequential test decompressors with fast variable wide spreading","authors":"O. Novák, Jiri Jenícek, M. Rozkovec","doi":"10.1109/DDECS.2016.7482454","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482454","url":null,"abstract":"Usually, test pattern decompressors with dynamic reseeding are reset before starting a new test pattern decoding. The first few scan chain slices are then filled with test vectors that have lower decodability as the number of free variables is limited by the test access mechanism bandwidth. We have found that it is possible to increase the number of free variables in the equations describing the care bits encoding by fast creating and wide spreading as many as possible independent linear combinations of the tester bits and using them for the scan chain loading. We propose a decompressor combining a combinational linear decompressor and an LFSR like automaton that effectively distributes the free variables within the test pattern. The proposed test pattern decompressor outperforms the de-codability of other decompressors with similar hardware overhead and it reduces the test time due to a possible reduction of the decompressor preloading.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130115578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-20DOI: 10.1109/DDECS.2016.7482442
J. Brenkus, V. Stopjaková, L. Nagy, D. Arbet
An alternative method of fault simulation is presented in this paper. The proposed method is based on impedance calculations in the circuit under test. Calculation time and other properties of the method are addressed and evaluated. Possible application and results evaluation are demonstrated on an experimental circuit. This method could improve the test development time and quality.
{"title":"Impedance calculation based method for AC fault analysis of mixed-signal circuits","authors":"J. Brenkus, V. Stopjaková, L. Nagy, D. Arbet","doi":"10.1109/DDECS.2016.7482442","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482442","url":null,"abstract":"An alternative method of fault simulation is presented in this paper. The proposed method is based on impedance calculations in the circuit under test. Calculation time and other properties of the method are addressed and evaluated. Possible application and results evaluation are demonstrated on an experimental circuit. This method could improve the test development time and quality.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134510214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-20DOI: 10.1109/DDECS.2016.7482440
Gökçe Aydos, G. Fey
Local triple modular redundancy (LTMR) is often the first choice to harden a flash-based FPGA application against soft errors in space. Unfortunately, LTMR leads to at least 300% area overhead. We propose a parity-based error detection approach, to use the limited resources of space-proven flash-based FPGAs more area-efficiently; this method can be the key for fitting the application onto the FPGA. A drawback of parity-based hardening is the significant impact on the critical path. To alleviate this error detection latency, pipeline structures in the design can be utilized. According to our results, this eliminates from 22% to 65% of the critical path overhead of the unpipelined error detection. Compared with LTMR, the new approach increases the critical path overhead of LTMR by a factor varying from 2 to 7.
{"title":"Exploiting error detection latency for parity-based soft error detection","authors":"Gökçe Aydos, G. Fey","doi":"10.1109/DDECS.2016.7482440","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482440","url":null,"abstract":"Local triple modular redundancy (LTMR) is often the first choice to harden a flash-based FPGA application against soft errors in space. Unfortunately, LTMR leads to at least 300% area overhead. We propose a parity-based error detection approach, to use the limited resources of space-proven flash-based FPGAs more area-efficiently; this method can be the key for fitting the application onto the FPGA. A drawback of parity-based hardening is the significant impact on the critical path. To alleviate this error detection latency, pipeline structures in the design can be utilized. According to our results, this eliminates from 22% to 65% of the critical path overhead of the unpipelined error detection. Compared with LTMR, the new approach increases the critical path overhead of LTMR by a factor varying from 2 to 7.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128407840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-20DOI: 10.1109/DDECS.2016.7482478
Róbert Tamási, M. Siebert, E. Gramatová, P. Fiser
Technology scaling and manufacturing process affect the performance of digital circuits, making them more vulnerable to environmental influences. Some defects are manifested as delay faults. Some various factors have impact to signal propagation delay. A new method is presented for determining factors impact measurement on the path delay in the digital circuits. The method is focused to find the best weights of the factors used as parameters for the PaCGen (Parameterized Critical Path Generator) system. PaCGen is used for critical paths selection based on static timing analysis data with impact of factors to propagation delay. Experimental results are provided using the ISCAS'89 benchmark circuits.
{"title":"A new method for path criticality calculation","authors":"Róbert Tamási, M. Siebert, E. Gramatová, P. Fiser","doi":"10.1109/DDECS.2016.7482478","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482478","url":null,"abstract":"Technology scaling and manufacturing process affect the performance of digital circuits, making them more vulnerable to environmental influences. Some defects are manifested as delay faults. Some various factors have impact to signal propagation delay. A new method is presented for determining factors impact measurement on the path delay in the digital circuits. The method is focused to find the best weights of the factors used as parameters for the PaCGen (Parameterized Critical Path Generator) system. PaCGen is used for critical paths selection based on static timing analysis data with impact of factors to propagation delay. Experimental results are provided using the ISCAS'89 benchmark circuits.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130430237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-20DOI: 10.1109/DDECS.2016.7482456
T. Polzer, A. Steininger
In digital CMOS essentially all sequential function blocks may get metastable in one way or another, when provided with marginal inputs. Most often the result is a delayed reaction at the output, which, in a synchronous design, potentially violates the timing assumptions. Therefore metastable behavior is often characterized by the Mean Time Between Upset (MTBU), which reflects the expected interval between such violations on a statistical base. However, not all designs are synchronous - there are even sequential elements specifically intended for use in context with elastic timing, such as the mutual exclusion element or the Muller C-element. For these a characterization via MTBU is not useful; but on the other hand there seem to be no reasonable alternatives. Therefore in this paper we propose the use of the delay graph (over the relevant quantity that causes metastability when becoming marginal) for this purpose. We elaborate its correspondence with the usual MTBU graph and the metastability parameters, namely tau and T0. As a proof of concept we apply our strategy to a set of sequential elements, like D-latch, RS-latch, Muller C-element and mutex and discuss the differences we identified.
在数字CMOS中，当提供边缘输入时，基本上所有顺序功能块都可以以这样或那样的方式变得亚稳。大多数情况下，结果是输出处的延迟反应，在同步设计中，这可能违反了时间假设。因此，亚稳行为通常用平均扰动间隔时间(Mean Time Between Upset, MTBU)来表征，它在统计基础上反映了这些违规之间的预期间隔。然而，并不是所有的设计都是同步的——甚至有专门用于弹性时序的顺序元素，比如互斥元素或Muller c元素。对于这些，通过MTBU进行表征是没有用的;但另一方面，似乎没有合理的选择。因此，在本文中，我们建议为此目的使用延迟图(在成为边缘时导致亚稳态的相关量之上)。我们详细阐述了它与通常的MTBU图和亚稳态参数，即tau和T0的对应关系。作为概念证明，我们将我们的策略应用于一组顺序元件，如D-latch, RS-latch, Muller C-element和互斥锁，并讨论了我们发现的差异。
{"title":"A general approach for comparing metastable behavior of digital CMOS gates","authors":"T. Polzer, A. Steininger","doi":"10.1109/DDECS.2016.7482456","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482456","url":null,"abstract":"In digital CMOS essentially all sequential function blocks may get metastable in one way or another, when provided with marginal inputs. Most often the result is a delayed reaction at the output, which, in a synchronous design, potentially violates the timing assumptions. Therefore metastable behavior is often characterized by the Mean Time Between Upset (MTBU), which reflects the expected interval between such violations on a statistical base. However, not all designs are synchronous - there are even sequential elements specifically intended for use in context with elastic timing, such as the mutual exclusion element or the Muller C-element. For these a characterization via MTBU is not useful; but on the other hand there seem to be no reasonable alternatives. Therefore in this paper we propose the use of the delay graph (over the relevant quantity that causes metastability when becoming marginal) for this purpose. We elaborate its correspondence with the usual MTBU graph and the metastability parameters, namely tau and T0. As a proof of concept we apply our strategy to a set of sequential elements, like D-latch, RS-latch, Muller C-element and mutex and discuss the differences we identified.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125551561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work presents a low-voltage indoor energy harvesting using photovoltaic cell. The system doesn't use a dc-dc converter to boost the output voltage so that large external inductors and large capacitors are eliminated. A rechargeable battery is connected to the output for storing the energy. No other external components are needed in the system. A test chip is implemented using a 0.18um CMOS process with a chip area of 0.85×0.85mm2 and a power consumption of 272uW. This solar cell provides a voltage of 0.4V~0.55V to the test chip at a minimum illumination of 61~625 Lux. A maximum efficiency of 54% can be obtained when the supply voltage is 0.5V.
{"title":"Low-voltage indoor energy harvesting using photovoltaic cell","authors":"Hong-Yi Huang, Shao-Zu Yen, Jhen-Hong Chen, Hao-Chiao Hong, Kuo-Hsing Cheng","doi":"10.1109/DDECS.2016.7482472","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482472","url":null,"abstract":"This work presents a low-voltage indoor energy harvesting using photovoltaic cell. The system doesn't use a dc-dc converter to boost the output voltage so that large external inductors and large capacitors are eliminated. A rechargeable battery is connected to the output for storing the energy. No other external components are needed in the system. A test chip is implemented using a 0.18um CMOS process with a chip area of 0.85×0.85mm2 and a power consumption of 272uW. This solar cell provides a voltage of 0.4V~0.55V to the test chip at a minimum illumination of 61~625 Lux. A maximum efficiency of 54% can be obtained when the supply voltage is 0.5V.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126390480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-20DOI: 10.1109/DDECS.2016.7482469
Igor Butryn, Krzysztof Siwiec, Jakub Kopanski, W. Pleskacz
The paper presents an Integer-N phase locked loop (PLL) for Bluetooth receiver implemented in CMOS 130 nm technology. The presented phase locked loop consists of an LC quadrature voltage controlled oscillator with capacitor bank, a tri-state phase-frequency detector with charge pump, a third order passive filter and a programmable divider. The PLL has a supply voltage of 1.2 V and dissipates 2.4 mW. The output frequency range of the phase locked loop is from 2.2 GHz to 2.8 GHz and phase noise is equal -124 dBm/Hz at 3 MHz from carrier frequency.
{"title":"Integer-N phase locked loop for bluetooth receiver in CMOS 130 nm technology","authors":"Igor Butryn, Krzysztof Siwiec, Jakub Kopanski, W. Pleskacz","doi":"10.1109/DDECS.2016.7482469","DOIUrl":"https://doi.org/10.1109/DDECS.2016.7482469","url":null,"abstract":"The paper presents an Integer-N phase locked loop (PLL) for Bluetooth receiver implemented in CMOS 130 nm technology. The presented phase locked loop consists of an LC quadrature voltage controlled oscillator with capacitor bank, a tri-state phase-frequency detector with charge pump, a third order passive filter and a programmable divider. The PLL has a supply voltage of 1.2 V and dissipates 2.4 mW. The output frequency range of the phase locked loop is from 2.2 GHz to 2.8 GHz and phase noise is equal -124 dBm/Hz at 3 MHz from carrier frequency.","PeriodicalId":404733,"journal":{"name":"2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116068546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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