Comparative Analysis of CMOS Latch-Driver Circuits for Current-Steering Digital-to-Analog Converters

Abstract

In this paper a comparative analysis of single- and dual-phase-clocked latch-driver circuits aimed at current-steering (CS) digital-to-analog converters (DACs) is presented. The design metrics of power consumption, propagation and switching delay as well as their product are considered. Moreover, an alternative latch-driver is proposed to sustain low-power consumption with short switching-delay. A 65 nm CMOS process is used and the results are obtained from post-layout simulations. In the analysis, dual-phase-clocked circuits consume about 2.4 x more power consumption and report 5.9 x shorter switching-delay with respect to the single-phase-clocked circuits. The proposed latch-driver consumes about 1.6 x more power with maintained switching-delay as the dual-phase-clocked solutions that leads to a reduction in the power-delay product of 25% and the lowest power-switching-delay product in the supply range 0.8-1.2 V.