Pub Date : 2022-06-23DOI: 10.23919/mixdes55591.2022.9837970
Magdalena Rosol, P. Kmon
This paper presents the design and postlayout simu-lation results of 8-bit analog-to-digital converter (ADC) dedicated to multichannel biomedical integrated recording system. The integrated circuit is implemented in CMOS 40 nm process and has been recently received from fabrication. The proposed ADC is based on charge redistribution technique utilizing only two capacitors. The designed ADC converts analog signals provided from eight chopper based amplifiers, achieves sampling rate up to 1 M S / s and occupies only 0. 0033m m2 of silicon area. The peak DNL and INL are −0.6 and −1.4 LSB respectively. This paper presents particular blocks' detailed analysis as well as their postlayout simulation results.
本文介绍了多通道生物医学综合记录系统专用的8位模数转换器(ADC)的设计和布局后仿真结果。该集成电路采用CMOS 40纳米工艺实现，最近已完成制造。所提出的ADC基于电荷再分配技术，仅利用两个电容器。所设计的ADC转换来自8个斩波放大器的模拟信号，实现高达1m S / S的采样率，仅占用0。硅面积为0033m m2。峰值DNL和INL分别为- 0.6和- 1.4 LSB。本文给出了具体模块的详细分析及其布局后仿真结果。
{"title":"8-bit Low-Power, Low-Area SAR ADC for Biomedical Multichannel Integrated Recording System in CMOS 40nm","authors":"Magdalena Rosol, P. Kmon","doi":"10.23919/mixdes55591.2022.9837970","DOIUrl":"https://doi.org/10.23919/mixdes55591.2022.9837970","url":null,"abstract":"This paper presents the design and postlayout simu-lation results of 8-bit analog-to-digital converter (ADC) dedicated to multichannel biomedical integrated recording system. The integrated circuit is implemented in CMOS 40 nm process and has been recently received from fabrication. The proposed ADC is based on charge redistribution technique utilizing only two capacitors. The designed ADC converts analog signals provided from eight chopper based amplifiers, achieves sampling rate up to 1 M S / s and occupies only 0. 0033m m2 of silicon area. The peak DNL and INL are −0.6 and −1.4 LSB respectively. This paper presents particular blocks' detailed analysis as well as their postlayout simulation results.","PeriodicalId":356244,"journal":{"name":"2022 29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115597932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-23DOI: 10.23919/mixdes55591.2022.9838144
{"title":"Medical Applications","authors":"","doi":"10.23919/mixdes55591.2022.9838144","DOIUrl":"https://doi.org/10.23919/mixdes55591.2022.9838144","url":null,"abstract":"","PeriodicalId":356244,"journal":{"name":"2022 29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121243367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-23DOI: 10.23919/mixdes55591.2022.9838351
{"title":"Single Processing","authors":"","doi":"10.23919/mixdes55591.2022.9838351","DOIUrl":"https://doi.org/10.23919/mixdes55591.2022.9838351","url":null,"abstract":"","PeriodicalId":356244,"journal":{"name":"2022 29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123789589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-23DOI: 10.23919/mixdes55591.2022.9837990
Oscar Morales Chacon, J. Wikner, A. Alvandpour, L. Siek
In this paper a comparative analysis of single- and dual-phase-clocked latch-driver circuits aimed at current-steering (CS) digital-to-analog converters (DACs) is presented. The design metrics of power consumption, propagation and switching delay as well as their product are considered. Moreover, an alternative latch-driver is proposed to sustain low-power consumption with short switching-delay. A 65 nm CMOS process is used and the results are obtained from post-layout simulations. In the analysis, dual-phase-clocked circuits consume about 2.4 x more power consumption and report 5.9 x shorter switching-delay with respect to the single-phase-clocked circuits. The proposed latch-driver consumes about 1.6 x more power with maintained switching-delay as the dual-phase-clocked solutions that leads to a reduction in the power-delay product of 25% and the lowest power-switching-delay product in the supply range 0.8-1.2 V.
{"title":"Comparative Analysis of CMOS Latch-Driver Circuits for Current-Steering Digital-to-Analog Converters","authors":"Oscar Morales Chacon, J. Wikner, A. Alvandpour, L. Siek","doi":"10.23919/mixdes55591.2022.9837990","DOIUrl":"https://doi.org/10.23919/mixdes55591.2022.9837990","url":null,"abstract":"In this paper a comparative analysis of single- and dual-phase-clocked latch-driver circuits aimed at current-steering (CS) digital-to-analog converters (DACs) is presented. The design metrics of power consumption, propagation and switching delay as well as their product are considered. Moreover, an alternative latch-driver is proposed to sustain low-power consumption with short switching-delay. A 65 nm CMOS process is used and the results are obtained from post-layout simulations. In the analysis, dual-phase-clocked circuits consume about 2.4 x more power consumption and report 5.9 x shorter switching-delay with respect to the single-phase-clocked circuits. The proposed latch-driver consumes about 1.6 x more power with maintained switching-delay as the dual-phase-clocked solutions that leads to a reduction in the power-delay product of 25% and the lowest power-switching-delay product in the supply range 0.8-1.2 V.","PeriodicalId":356244,"journal":{"name":"2022 29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126413656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-23DOI: 10.23919/mixdes55591.2022.9838216
C. Roemer, G. Darbandy, M. Schwarz, J. Trommer, M. Simon, A. Heinzig, T. Mikolajick, W. Weber, B. Iñíguez, A. Kloes
Reconfigurable field-effect transistors come with an additional gate contact, which leads to challenges for compact modeling. In this work, a closed-form and physics-based DC model is derived for those devices, which combines the injection current over the Schottky barriers with the resistance-effects of partially ungated device channel segments or long channel devices. The model verification is done by comparing the results to TCAD simulations and measurements.
{"title":"Compact Modeling of Channel-Resistance Effects in Reconfigurable Field-Effect Transistors","authors":"C. Roemer, G. Darbandy, M. Schwarz, J. Trommer, M. Simon, A. Heinzig, T. Mikolajick, W. Weber, B. Iñíguez, A. Kloes","doi":"10.23919/mixdes55591.2022.9838216","DOIUrl":"https://doi.org/10.23919/mixdes55591.2022.9838216","url":null,"abstract":"Reconfigurable field-effect transistors come with an additional gate contact, which leads to challenges for compact modeling. In this work, a closed-form and physics-based DC model is derived for those devices, which combines the injection current over the Schottky barriers with the resistance-effects of partially ungated device channel segments or long channel devices. The model verification is done by comparing the results to TCAD simulations and measurements.","PeriodicalId":356244,"journal":{"name":"2022 29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"196 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131991191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-23DOI: 10.23919/mixdes55591.2022.9838323
Denis Sami, D. Levski, G. Meynants, Martin Waeny, Nikolai Dimitrov, Georgi Bochev, R. Kandilarov
A readout system designed for characterizing CMOS active pixels for imaging with global or rolling shutter operation is presented. The readout chain consists of an ana-log and digital column-parallel front end to increase readout speed. The column readout circuitry shown in detail includes a Programmable Gain Amplifier (PGA) with Correlated Double Sampling (CDS) and offset cancelling features. Programmable row and global drivers which improve the system flexibility have been discussed. The presented readout design was silicon proven on a 0.11um Front Side Illumination CMOS process in reading out 7T charge domain pixels with single-snapshot High-Dynamic Range (HDR) features.
介绍了一种用于全局或滚动快门成像的CMOS有源像素的读出系统。读出链由反对数和数字列并行前端组成，以提高读出速度。详细显示的列读出电路包括一个具有相关双采样(CDS)和偏移抵消功能的可编程增益放大器(PGA)。讨论了提高系统灵活性的可编程行和全局驱动。所提出的读出设计在0.11um Front Side Illumination CMOS工艺上进行了硅验证，可读出具有单快照高动态范围(HDR)特征的7T电荷域像素。
{"title":"A Flexible CMOS Test-Pixel Readout System","authors":"Denis Sami, D. Levski, G. Meynants, Martin Waeny, Nikolai Dimitrov, Georgi Bochev, R. Kandilarov","doi":"10.23919/mixdes55591.2022.9838323","DOIUrl":"https://doi.org/10.23919/mixdes55591.2022.9838323","url":null,"abstract":"A readout system designed for characterizing CMOS active pixels for imaging with global or rolling shutter operation is presented. The readout chain consists of an ana-log and digital column-parallel front end to increase readout speed. The column readout circuitry shown in detail includes a Programmable Gain Amplifier (PGA) with Correlated Double Sampling (CDS) and offset cancelling features. Programmable row and global drivers which improve the system flexibility have been discussed. The presented readout design was silicon proven on a 0.11um Front Side Illumination CMOS process in reading out 7T charge domain pixels with single-snapshot High-Dynamic Range (HDR) features.","PeriodicalId":356244,"journal":{"name":"2022 29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130108569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-23DOI: 10.23919/mixdes55591.2022.9837994
M. Jankowski, J. Nazdrowicz, P. Zając, Piotr Amrozik, M. Szermer, C. Maj, G. Jabłoński
The presented work provides results and discusses implications for introductory comparison of test results of temperature dependence of the integrated semiconductor system designed as a part of a system for imbalance disorder monitoring. Two types of test chips are taken into account, each of them mounted on two PCB versions, provided by different manufacturers. The findings provided by comparative analysis of results obtained for previously performed test sessions are presented and discussed. Their significance paired with the low number of available test setups (chip and PCB variants) point to further analysis steps, which are highlighted and their progress summarized.
{"title":"Observation of Readout Temperature Dependence and Its Variability for the MEMS and ASIC System Specimens and Their PCB Testbenches","authors":"M. Jankowski, J. Nazdrowicz, P. Zając, Piotr Amrozik, M. Szermer, C. Maj, G. Jabłoński","doi":"10.23919/mixdes55591.2022.9837994","DOIUrl":"https://doi.org/10.23919/mixdes55591.2022.9837994","url":null,"abstract":"The presented work provides results and discusses implications for introductory comparison of test results of temperature dependence of the integrated semiconductor system designed as a part of a system for imbalance disorder monitoring. Two types of test chips are taken into account, each of them mounted on two PCB versions, provided by different manufacturers. The findings provided by comparative analysis of results obtained for previously performed test sessions are presented and discussed. Their significance paired with the low number of available test setups (chip and PCB variants) point to further analysis steps, which are highlighted and their progress summarized.","PeriodicalId":356244,"journal":{"name":"2022 29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115575006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-23DOI: 10.23919/mixdes55591.2022.9838126
Dariusz Wąsicki, T. Luba
The article discusses the possibilities of the application of logic synthesis methods in data mining tasks. In particular, the method of reducing attributes and the method of inducing decision rules is considered. It is shown that by applying specialized logic synthesis methods, these issues can be effectively improved and successfully used for solving data mining tasks. In justification of the advisability of such proceedings, the patient's diagnosis with the possibility of eliminating troublesome tests is discussed.
{"title":"Data Analysis and Mining Using Logical Synthesis Methods","authors":"Dariusz Wąsicki, T. Luba","doi":"10.23919/mixdes55591.2022.9838126","DOIUrl":"https://doi.org/10.23919/mixdes55591.2022.9838126","url":null,"abstract":"The article discusses the possibilities of the application of logic synthesis methods in data mining tasks. In particular, the method of reducing attributes and the method of inducing decision rules is considered. It is shown that by applying specialized logic synthesis methods, these issues can be effectively improved and successfully used for solving data mining tasks. In justification of the advisability of such proceedings, the patient's diagnosis with the possibility of eliminating troublesome tests is discussed.","PeriodicalId":356244,"journal":{"name":"2022 29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122010544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-23DOI: 10.23919/mixdes55591.2022.9837959
M. Fino
Over the last decades nanoelectronics have face an unprecedent evolution. Not only have the so-called conventional devices faced the development of new Mosfet device structures enabling the implementation of ever smaller device sizes operating at higher frequencies, but new unconventional devices have emerged as well. Also, the possibility of integrating intelligent nano sensors and actuators yields the possibility to modify our everyday life through cyber-physical systems. On the other hand, the application of these cyber-physical systems to a wide range of application domains, is also fueling the development of new devices with ever demanding specifications. This paper deals with the opportunities and challenges for nanoelectronics in their application in Cyber-physical systems
{"title":"Nanoelectronic Challenges and Opportunities for Cyber-Physical Systems","authors":"M. Fino","doi":"10.23919/mixdes55591.2022.9837959","DOIUrl":"https://doi.org/10.23919/mixdes55591.2022.9837959","url":null,"abstract":"Over the last decades nanoelectronics have face an unprecedent evolution. Not only have the so-called conventional devices faced the development of new Mosfet device structures enabling the implementation of ever smaller device sizes operating at higher frequencies, but new unconventional devices have emerged as well. Also, the possibility of integrating intelligent nano sensors and actuators yields the possibility to modify our everyday life through cyber-physical systems. On the other hand, the application of these cyber-physical systems to a wide range of application domains, is also fueling the development of new devices with ever demanding specifications. This paper deals with the opportunities and challenges for nanoelectronics in their application in Cyber-physical systems","PeriodicalId":356244,"journal":{"name":"2022 29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128796952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-23DOI: 10.23919/mixdes55591.2022.9838120
J. Nazdrowicz, M. Jankowski, P. Błaszczyk
The basic foundation for obtaining maximum power is reaching the maximum operating point (Maximum Power Point), which makes it the highest possible power produced by the panel in the given irradiance and temperature conditions. Achieving this power requires adjusting the voltage in the work cycle, which unfortunately requires a kind of “search” by “sampling” the value of the instantaneous power at a given voltage. However, it takes a certain time to reach the maximum power, which implies power losses. Another aspect to consider here is the power loss associated with rising temperature (Maximum Power Point shifts towards lower values). Therefore, these two aspects constitute the theme of this work.
{"title":"Analysis of Photovoltaics Performance Under Variable Conditions","authors":"J. Nazdrowicz, M. Jankowski, P. Błaszczyk","doi":"10.23919/mixdes55591.2022.9838120","DOIUrl":"https://doi.org/10.23919/mixdes55591.2022.9838120","url":null,"abstract":"The basic foundation for obtaining maximum power is reaching the maximum operating point (Maximum Power Point), which makes it the highest possible power produced by the panel in the given irradiance and temperature conditions. Achieving this power requires adjusting the voltage in the work cycle, which unfortunately requires a kind of “search” by “sampling” the value of the instantaneous power at a given voltage. However, it takes a certain time to reach the maximum power, which implies power losses. Another aspect to consider here is the power loss associated with rising temperature (Maximum Power Point shifts towards lower values). Therefore, these two aspects constitute the theme of this work.","PeriodicalId":356244,"journal":{"name":"2022 29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"141 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114012988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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