Sungsam Lee, Jong-Woo Park, Kwangwook Lee, S. Jang, Junhong Lee, H. Byun, Ilgweon Kim, Yongjin Choi, M.S. Shim, D. Song, Joosung Park, Tae-woo Lee, D.W. Shin, G. Jin, Kinam Kim
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引用次数: 0
Abstract
A new active isolation structure, LatEx (lateral-extended) active, which exploits recess channel transistors, is proposed. By realizing the LatEx active, data retention time enhancement was successfully achieved in 60 nm technology node DRAM by virtue of reduced source/drain area and improved subthreshold slope due to decreased cross-sectional area of top trench profile and vertical bottom trench process. In this paper, LatEx active coupled with SRCAT is proved to be suitable for sub 60 nm DRAM cell array transistor technology.
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