Digital and Analog Performance of Gate Inside P-Type Junctionless Transistor (GI-JLT)

Abstract

In this paper, digital and analog performance of p-type Gate Inside Junctionless Transistor (GI-JLT) is demonstrated for the first time by using 3-D Bohm Quantum Potential (BQP) transport device simulation to evaluate its use in future CMOS technology. Digital performance analysis exhibits a favourable on/off current ratio and better short-channel characteristics than a gate-all-around (GAA-JLT) junctionless device. Ion improvement by a factor of 3, Ioff reduction by a factor of 10, DIBL is minimized by 34% with slight reduction in subthreshold slope. In analog performance, p-type GI-JLT shows improvement of transconductance (gm) by a multiple of 3, similarly Transconductance generation factor (TGF) (gm/Ids) gets improved and cutoff frequency (fT ) showed improvement by 60% as compared with GAA-JLT. Larger gate electrostatic control is responsible for analog and digital performance improvement of GI-JLT.