Integration of MIM capacitors with low-k/Cu process for 90 nm analog circuit applications

Abstract

Integration of MIM capacitors into 90 nm mixed-signal applications is demonstrated for the first time with the testing vehicle of AD converter using low-k (k=2.7) Cu dual damascene process. To obtain high resolution MIM capacitor, process such as electrode etching and CMP of upper Cu line was carefully optimized. The optimized process condition yields more reliable MIM capacitors with less parasitic components. The parasitic capacitance caused by surrounding upper metal interconnect gives significant effect for IMD thickness less than 300 nm. For parasitic capacitance-free MIM capacitor, a landing-metal type is suggested, and parasitic capacitance is reduced more than 60% compared with conventional capacitor structure.