Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219761
J. Joyner, R. Venkatesan, J.A. Davis, J. Meindl
An interconnect distribution for a system utilizing liquid diagonal routing is rigorously derived. Using the distribution in conjunction with a wiring layer assignment algorithm, the limits of clock frequency and area improvements are quantified as a function of wiring efficiency, the ratio of utilized wiring area to those available. A liquid-routed system with only a 28% wiring efficiency is equivalent to an orthogonally routed system with a 40% wiring efficiency. A wiring efficiency of a liquid-routed system below 28% results in an inferior design in regards to clock frequency and/or required metal resources. If a 40% wiring efficiency is maintained, however, the power-constrained clock frequency can be increased by 38% with a 69% reduction in area, or the power-density-constrained area can be reduced by 75% with a 47% reduction in power. Liquid diagonal routing promises improvements to both area and clock frequency if the wiring efficiency is maintained above roughly 30%.
{"title":"The limits of system improvement through liquid diagonal routing of interconnects","authors":"J. Joyner, R. Venkatesan, J.A. Davis, J. Meindl","doi":"10.1109/IITC.2003.1219761","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219761","url":null,"abstract":"An interconnect distribution for a system utilizing liquid diagonal routing is rigorously derived. Using the distribution in conjunction with a wiring layer assignment algorithm, the limits of clock frequency and area improvements are quantified as a function of wiring efficiency, the ratio of utilized wiring area to those available. A liquid-routed system with only a 28% wiring efficiency is equivalent to an orthogonally routed system with a 40% wiring efficiency. A wiring efficiency of a liquid-routed system below 28% results in an inferior design in regards to clock frequency and/or required metal resources. If a 40% wiring efficiency is maintained, however, the power-constrained clock frequency can be increased by 38% with a 69% reduction in area, or the power-density-constrained area can be reduced by 75% with a 47% reduction in power. Liquid diagonal routing promises improvements to both area and clock frequency if the wiring efficiency is maintained above roughly 30%.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117194493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219734
S. Smith, G. Book, W. Li, Y. Sun, P. Gillespie, M. Tuominen, K. Pfeifer
A 2.7 nm ALD WN/sub x/C/sub y/ copper barrier was integrated into fully functional backend dual-damascene devices built in SiO/sub 2/ on 200-mm wafers at International Sematech. Electromigration results were extraordinary, with average time to failure more than 10 times longer than standard PVD Ta. Electrical and physical results suggest that ultrathin WN/sub x/C/sub Y/ is an excellent copper barrier and meets the requirements for integration, including: Via resistance, electromigration, barrier integrity, film continuity, etc.
{"title":"The application of ALD WN/sub x/C/sub y/ as a copper diffusion barrier","authors":"S. Smith, G. Book, W. Li, Y. Sun, P. Gillespie, M. Tuominen, K. Pfeifer","doi":"10.1109/IITC.2003.1219734","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219734","url":null,"abstract":"A 2.7 nm ALD WN/sub x/C/sub y/ copper barrier was integrated into fully functional backend dual-damascene devices built in SiO/sub 2/ on 200-mm wafers at International Sematech. Electromigration results were extraordinary, with average time to failure more than 10 times longer than standard PVD Ta. Electrical and physical results suggest that ultrathin WN/sub x/C/sub Y/ is an excellent copper barrier and meets the requirements for integration, including: Via resistance, electromigration, barrier integrity, film continuity, etc.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114168421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219701
K. Ishikawa, T. Iwasaki, T. Fujii, N. Nakajima, M. Miyauchi, T. Ohshima, J. Noguchi, H. Aoki, T. Saito
In this paper, we discuss the effect of adhesion strength between TaN/Ta barrier and copper (Cu) upon the reliability of dual-damascene Cu interconnects as well as the effect of stepcoverage. The ionized metal bias sputtering (IMBS) method was applied to TaN/Ta barrier and Cu seed formation of 0.13 /spl mu/m-node dual-damascene Cu interconnects and the electromigration and stress migration characteristics were successfully improved.
{"title":"Impact of metal deposition process upon reliability of dual-damascene copper interconnects","authors":"K. Ishikawa, T. Iwasaki, T. Fujii, N. Nakajima, M. Miyauchi, T. Ohshima, J. Noguchi, H. Aoki, T. Saito","doi":"10.1109/IITC.2003.1219701","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219701","url":null,"abstract":"In this paper, we discuss the effect of adhesion strength between TaN/Ta barrier and copper (Cu) upon the reliability of dual-damascene Cu interconnects as well as the effect of stepcoverage. The ionized metal bias sputtering (IMBS) method was applied to TaN/Ta barrier and Cu seed formation of 0.13 /spl mu/m-node dual-damascene Cu interconnects and the electromigration and stress migration characteristics were successfully improved.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"28 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129759163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219731
P. Zarkesh-Ha, P. Wright, S. Lakshminarayanan, C. Cheng, W. Loh, W. Lynch
Based on the marketing, methodology, and manufacturing requirements of ASIC products, an optimum back-end process for high-density ASIC chips in a 90 nm technology is proposed. The chip size for high-density ASIC chips has stayed roughly constant between 7 and 14 mm on a side. High-density chips are achieved with tight pitch for all routing levels. Optimum performance is obtained with a thinner metal 2 and 3 Cu thickness of 0.25 versus 0.35 /spl mu/m for the higher levels of metal.
{"title":"Backend process optimization for 90 nm high-density ASIC chips","authors":"P. Zarkesh-Ha, P. Wright, S. Lakshminarayanan, C. Cheng, W. Loh, W. Lynch","doi":"10.1109/IITC.2003.1219731","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219731","url":null,"abstract":"Based on the marketing, methodology, and manufacturing requirements of ASIC products, an optimum back-end process for high-density ASIC chips in a 90 nm technology is proposed. The chip size for high-density ASIC chips has stayed roughly constant between 7 and 14 mm on a side. High-density chips are achieved with tight pitch for all routing levels. Optimum performance is obtained with a thinner metal 2 and 3 Cu thickness of 0.25 versus 0.35 /spl mu/m for the higher levels of metal.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128676043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219735
Jung Hun Seo, B. Kim, Jong Myeong Lee, H. Park, J. Yun, Youngseop Rah, G. Choi, U. Chung, J. Moon
The new barrier metal structure using selective wetting layer was proposed. This process using physical vapor deposition (PVD) Ti as the controlling layer for conformal chemical vapor deposition (CVD) Al layer shows an excellent filling capability for deep small contact and good electrical properties as well as the remarkable surface morphology, which can be applied for the new metallization process such as metal contacts and via holes filling.
{"title":"The improved CVD-Al metallization for deep small contact filling using selective wetting process","authors":"Jung Hun Seo, B. Kim, Jong Myeong Lee, H. Park, J. Yun, Youngseop Rah, G. Choi, U. Chung, J. Moon","doi":"10.1109/IITC.2003.1219735","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219735","url":null,"abstract":"The new barrier metal structure using selective wetting layer was proposed. This process using physical vapor deposition (PVD) Ti as the controlling layer for conformal chemical vapor deposition (CVD) Al layer shows an excellent filling capability for deep small contact and good electrical properties as well as the remarkable surface morphology, which can be applied for the new metallization process such as metal contacts and via holes filling.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"31 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130636582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219742
G. Dixit, D. Padhi, S. Gandikota, J. Yahalom, S. Parikh, N. Yoshida, K. Shankaranarayanan, J. Chen, N. Maity, J. Yu
Various factors such as grain boundary/surface diffusion as well as structural properties of materials are known to affect the final electro-migration (EM) behavior of copper interconnections. Results presented in this paper show that the barrier layer has a strong influence in controlling the width of EM failure distributions. EM tests of samples with alternate barrier, fill and capping layers show that atomic layer chemical vapor deposited (ALCVD) barrier and/or metallic cap layers are key to realize structures with superior EM lifetimes.
{"title":"Enhancing the electromigration resistance of copper interconnects","authors":"G. Dixit, D. Padhi, S. Gandikota, J. Yahalom, S. Parikh, N. Yoshida, K. Shankaranarayanan, J. Chen, N. Maity, J. Yu","doi":"10.1109/IITC.2003.1219742","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219742","url":null,"abstract":"Various factors such as grain boundary/surface diffusion as well as structural properties of materials are known to affect the final electro-migration (EM) behavior of copper interconnections. Results presented in this paper show that the barrier layer has a strong influence in controlling the width of EM failure distributions. EM tests of samples with alternate barrier, fill and capping layers show that atomic layer chemical vapor deposited (ALCVD) barrier and/or metallic cap layers are key to realize structures with superior EM lifetimes.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121503989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219711
K. Shakeri, J. Meindl
The supply voltage decrease and power density increase of future GSI chips demands accurate models for the IR-drop voltage. Compact physical IR-drop models are derived for two types of packages. These models help designers estimate the required amount of interconnects and package pins which need to be dedicated for power distribution. Comparison with SPICE simulations show less than 1% and 5% error for the wire-bond package and the area-array package, respectively.
{"title":"Compact physical IR-drop models for GSI power distribution networks","authors":"K. Shakeri, J. Meindl","doi":"10.1109/IITC.2003.1219711","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219711","url":null,"abstract":"The supply voltage decrease and power density increase of future GSI chips demands accurate models for the IR-drop voltage. Compact physical IR-drop models are derived for two types of packages. These models help designers estimate the required amount of interconnects and package pins which need to be dedicated for power distribution. Comparison with SPICE simulations show less than 1% and 5% error for the wire-bond package and the area-array package, respectively.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115740356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219723
M. Assous, J. Simon, L. Broussous, C. Bourlot, M. Fayolle, O. Louveau, A. Roman, E. Tabouret, H. Feldis, D. Louis, J. Torres
A dual hard mask, dual damascene architecture was developed to circumvent integration problems brought by porous ULK dielectric use. It was demonstrated that a via first strategy with adequately defined hard masks can improve patterning conditions.
{"title":"Porous dielectric dual damascene patterning issues for 65 nm node: can architecture bring a solution?","authors":"M. Assous, J. Simon, L. Broussous, C. Bourlot, M. Fayolle, O. Louveau, A. Roman, E. Tabouret, H. Feldis, D. Louis, J. Torres","doi":"10.1109/IITC.2003.1219723","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219723","url":null,"abstract":"A dual hard mask, dual damascene architecture was developed to circumvent integration problems brought by porous ULK dielectric use. It was demonstrated that a via first strategy with adequately defined hard masks can improve patterning conditions.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123660797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219714
L. Gosset, V. Arnal, C. Prindle, R. Hoofman, G. Verheijden, R. Daamen, L. Broussous, F. Fusalba, M. Assous, R. Chatterjee, J. Torres, D. Gravesteijn, K. Yu
The present paper deals with the different techniques investigated in the whole microelectronics community to integrate air cavities, usually known as air gaps, in-between copper lines for advanced interconnects. The different integration processes were split into two categories, i.e. (i) using a non-conformal CVD deposition inside patterned trenches and (ii) by removing a sacrificial material using a specific technological operation. Advantages and drawbacks of the different approaches will be discussed, including integration issues, manufacturability, and electrical performances. The aim of the paper is to sensitize the BEOL community on these specific approaches that now appear attractive considering the electrical performances required for 45 nm and below technological nodes.
{"title":"General review of issues and perspectives for advanced copper interconnections using air gap as ultra-low K material","authors":"L. Gosset, V. Arnal, C. Prindle, R. Hoofman, G. Verheijden, R. Daamen, L. Broussous, F. Fusalba, M. Assous, R. Chatterjee, J. Torres, D. Gravesteijn, K. Yu","doi":"10.1109/IITC.2003.1219714","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219714","url":null,"abstract":"The present paper deals with the different techniques investigated in the whole microelectronics community to integrate air cavities, usually known as air gaps, in-between copper lines for advanced interconnects. The different integration processes were split into two categories, i.e. (i) using a non-conformal CVD deposition inside patterned trenches and (ii) by removing a sacrificial material using a specific technological operation. Advantages and drawbacks of the different approaches will be discussed, including integration issues, manufacturability, and electrical performances. The aim of the paper is to sensitize the BEOL community on these specific approaches that now appear attractive considering the electrical performances required for 45 nm and below technological nodes.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122091133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-02DOI: 10.1109/IITC.2003.1219740
A. Rashid, S. Watanabe, T. Kikkawa
Crosstalks on local interconnect metal lines at high frequency have been evaluated for wireless interconnect on Si using monopole integrated antenna. For an antenna of length 3 mm, the maximum value of crosstalk on a victim line of same length and separated by a distance of 10 /spl mu/m was found to be -18 dB at 9 GHz. Large reduction in crosstalk is possible by operating the antenna slightly off the resonance point.
{"title":"Crosstalk isolation of monopole integrated antenna on Si for ULSI wireless interconnect","authors":"A. Rashid, S. Watanabe, T. Kikkawa","doi":"10.1109/IITC.2003.1219740","DOIUrl":"https://doi.org/10.1109/IITC.2003.1219740","url":null,"abstract":"Crosstalks on local interconnect metal lines at high frequency have been evaluated for wireless interconnect on Si using monopole integrated antenna. For an antenna of length 3 mm, the maximum value of crosstalk on a victim line of same length and separated by a distance of 10 /spl mu/m was found to be -18 dB at 9 GHz. Large reduction in crosstalk is possible by operating the antenna slightly off the resonance point.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"317 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123305246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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