A 500 MS/s 10-Bit Single-Channel SAR ADC with A Double-Rate Comparator

Abstract

This paper presents a 500 MS/s 10-bit single-channel SAR ADC with a reconfigurable double-rate comparator for enhanced operation speed. The proposed double-rate comparator effectively eliminates the delay caused by comparator reset from the critical path while consuming less power and reducing the clock frequency by half. A test chip is fabricated in a 28 nm FDSOI technology. Clocked at 500 MS/s, the proposed ADC achieves a SNDR of 52.7 dB and a SFDR of 62.49 dB at Nyquist with a power consumption of 1.18 mW, showing a Walden FOM of 6.7 fJ/conv.-step.