S. Morvan, F. Andrieu, M. Cassé, O. Weber, N. Xu, P. Perreau, J. Hartmann, J. Barbe, J. Mazurier, P. Nguyen, C. Fenouillet-Béranger, C. Tabone, L. Tosti, L. Brevard, A. Toffoli, F. Allain, D. Lafond, B. Nguyen, G. Ghibaudo, F. Boeuf, O. Faynot, T. Poiroux
{"title":"Efficiency of mechanical stressors in Planar FDSOI n and p MOSFETs down to 14nm gate length","authors":"S. Morvan, F. Andrieu, M. Cassé, O. Weber, N. Xu, P. Perreau, J. Hartmann, J. Barbe, J. Mazurier, P. Nguyen, C. Fenouillet-Béranger, C. Tabone, L. Tosti, L. Brevard, A. Toffoli, F. Allain, D. Lafond, B. Nguyen, G. Ghibaudo, F. Boeuf, O. Faynot, T. Poiroux","doi":"10.1109/VLSIT.2012.6242486","DOIUrl":null,"url":null,"abstract":"We fabricated highly stressed Fully Depleted Silicon-On-Insulator (FDSOI) n and pMOSFETs reaching I<sub>ON,n</sub>/I<sub>ON,p</sub>=1148/1014μA/μm drive current at I<sub>OFF,n</sub>/I<sub>OFF,p</sub>=55/16nA/μm leakage current (V<sub>DD</sub>=1V) with excellent V<sub>T</sub>-matching (A<sub>VT</sub> <; 1.5mV.μm). These short channel performances are well correlated and quantitatively explained by the effectiveness of strained SOI (sSOI), Contact-Etch-Stop-Layers (CESL) and SiGe raised sources and drains. sSOI improves I<sub>ON,n</sub> up to 22% and degrades SiGe sources and drains efficiency for pMOSFETs. However, 0° (<;110>;) orientation remains the best configuration for high-stress pMOSFETs and provides the best trade-off for CMOS.","PeriodicalId":266298,"journal":{"name":"2012 Symposium on VLSI Technology (VLSIT)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 Symposium on VLSI Technology (VLSIT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2012.6242486","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 16
Abstract
We fabricated highly stressed Fully Depleted Silicon-On-Insulator (FDSOI) n and pMOSFETs reaching ION,n/ION,p=1148/1014μA/μm drive current at IOFF,n/IOFF,p=55/16nA/μm leakage current (VDD=1V) with excellent VT-matching (AVT <; 1.5mV.μm). These short channel performances are well correlated and quantitatively explained by the effectiveness of strained SOI (sSOI), Contact-Etch-Stop-Layers (CESL) and SiGe raised sources and drains. sSOI improves ION,n up to 22% and degrades SiGe sources and drains efficiency for pMOSFETs. However, 0° (<;110>;) orientation remains the best configuration for high-stress pMOSFETs and provides the best trade-off for CMOS.
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