Process simulation and experiment for RC-parasitics in multilevel metallization

Abstract

An integrated computer-aided-design environment is presented which is suitable for interconnect process design. It displays device cross-sections and electrical performance parameters by linking information from layout, process flow, rigorous topography simulation, and electrical analysis. As a specific example, these CAD tools have been applied to a proposed planarization process to study the topographies resulting from different process parameters and layout mask designs. Exploratory electrical test structures have been developed to help demonstrate topography-induced increases in parasitic effects and to establish the validity of the simulation.<>