M. Noguchi, T. Ozaki, M. Aoki, T. Hamamoto, M. Habu, Y. Kato, Y. Takigami, T. Shibata, T. Nakasugi, H. Niiyama, K. Tokano, Y. Saito, T. Hoshi, S. Watanabe
{"title":"0.29-/spl mu/m/sup 2/ trench cell technologies for 1G-bit DRAMs with open/folded-bit-line layout and selective growth technique","authors":"M. Noguchi, T. Ozaki, M. Aoki, T. Hamamoto, M. Habu, Y. Kato, Y. Takigami, T. Shibata, T. Nakasugi, H. Niiyama, K. Tokano, Y. Saito, T. Hoshi, S. Watanabe","doi":"10.1109/VLSIT.1995.520895","DOIUrl":null,"url":null,"abstract":"We present substrate-plate-trench cell technologies for 1G-bit DRAMs. With an open/folded-bit-line layout, the smallest cell area of 0.29 /spl mu/m/sup 2/ was realized for a 0.20 /spl mu/m design rule. A pause time of 4.2 s at 85/spl deg/C and an activation energy of 0.70 eV were achieved for a 0.25-/spl mu/m/spl Phi//spl times/4-/spl mu/m trench capacitor. A new Si selective epitaxial growth (SEG) technique was developed to reduce connection formation between the capacitor and transistor to one fabrication step, and also reduce a distance between the trench and gate. The gate capacitors on the SEG showed a breakdown electric field over 11 MV/cm even when the distance was less than 0.1 /spl mu/m.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1995 Symposium on VLSI Technology. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1995.520895","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
We present substrate-plate-trench cell technologies for 1G-bit DRAMs. With an open/folded-bit-line layout, the smallest cell area of 0.29 /spl mu/m/sup 2/ was realized for a 0.20 /spl mu/m design rule. A pause time of 4.2 s at 85/spl deg/C and an activation energy of 0.70 eV were achieved for a 0.25-/spl mu/m/spl Phi//spl times/4-/spl mu/m trench capacitor. A new Si selective epitaxial growth (SEG) technique was developed to reduce connection formation between the capacitor and transistor to one fabrication step, and also reduce a distance between the trench and gate. The gate capacitors on the SEG showed a breakdown electric field over 11 MV/cm even when the distance was less than 0.1 /spl mu/m.
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