A 40 ns random access time low voltage 2Mbits EEPROM memory for embedded applications

J. Daga, Caroline Papaix, E. Racape, M. Combe, Vincent Sialelli, J. Guichaoua
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引用次数: 7

Abstract

2Mbits EEPROM memory has been designed using the ATMEL 0.18 /spl mu/m embedded technology. On silicon program and read access time measurements are given, and an optimized production testing flow is proposed.
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用于嵌入式应用的40 ns随机访问时间低电压2mb EEPROM存储器
采用ATMEL 0.18 /spl mu/m嵌入式技术设计了2mb EEPROM存储器。给出了硅程序和读访问时间的测量结果,并提出了优化的生产测试流程。
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ITRS commodity memory roadmap A testability-driven optimizer and wrapper generator for embedded memories Systematic memory test generation for DRAM defects causing two floating nodes A 40 ns random access time low voltage 2Mbits EEPROM memory for embedded applications Reducing test time of embedded SRAMs
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