Pub Date : 2003-07-28DOI: 10.1109/MTDT.2003.1222358
Z. Al-Ars, S. Hamdioui, A. V. Goor
Linked faults are very important for memory testing because they reduce the fault coverage of the tests. Their analysis has proven to be a source for new memory tests, characterized by an increased fault coverage for a given test time. This paper presents an analysis of linked faults, based on the concept of fault primitives, such that the whole space of linked faults is investigated, accounted for and validated. The paper also introduces a systematic way to develop tests for such faults.
{"title":"A fault primitive based analysis of linked faults in RAMs","authors":"Z. Al-Ars, S. Hamdioui, A. V. Goor","doi":"10.1109/MTDT.2003.1222358","DOIUrl":"https://doi.org/10.1109/MTDT.2003.1222358","url":null,"abstract":"Linked faults are very important for memory testing because they reduce the fault coverage of the tests. Their analysis has proven to be a source for new memory tests, characterized by an increased fault coverage for a given test time. This paper presents an analysis of linked faults, based on the concept of fault primitives, such that the whole space of linked faults is investigated, accounted for and validated. The paper also introduces a systematic way to develop tests for such faults.","PeriodicalId":412381,"journal":{"name":"Records of the 2003 International Workshop on Memory Technology, Design and Testing","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130409819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-28DOI: 10.1109/MTDT.2003.1222362
R. Barth
The ITRS (International Technology Roadmap for Semiconductors) roadmap is updated on a yearly basis to forecast industry silicon trends. The ITRS Test Working Group (TWG) identifies the key trends that will have an impact on device test and summarizes them to provide direction to test suppliers. The commodity memory roadmap is a key part of that forecast and covers discrete and embedded DRAM and Flash. The material in this paper represents a very early look at the potential commodity memory roadmap due for release in November of 2003 and is based upon the 2002 roadmap.
{"title":"ITRS commodity memory roadmap","authors":"R. Barth","doi":"10.1109/MTDT.2003.1222362","DOIUrl":"https://doi.org/10.1109/MTDT.2003.1222362","url":null,"abstract":"The ITRS (International Technology Roadmap for Semiconductors) roadmap is updated on a yearly basis to forecast industry silicon trends. The ITRS Test Working Group (TWG) identifies the key trends that will have an impact on device test and summarizes them to provide direction to test suppliers. The commodity memory roadmap is a key part of that forecast and covers discrete and embedded DRAM and Flash. The material in this paper represents a very early look at the potential commodity memory roadmap due for release in November of 2003 and is based upon the 2002 roadmap.","PeriodicalId":412381,"journal":{"name":"Records of the 2003 International Workshop on Memory Technology, Design and Testing","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114111121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-28DOI: 10.1109/MTDT.2003.1222359
J. Vollrath
The exact placement of the data output eye for high speed single and double data rate (SDR, DDR) synchronous dynamic random access memories (SDRAM) allows high speed operation. For the timing measurement method via current presented in this paper the tester drives data at the same time as the device. The current consumption of the device is depending on the overlap of the tester output waveform and the waveform of the data driven by the device under test (DUT). This paper presents the measurement method and results from a 128M x4 SDRAM and compares them to a traditional approach using a data strobe.
{"title":"Output timing measurement using an Idd method","authors":"J. Vollrath","doi":"10.1109/MTDT.2003.1222359","DOIUrl":"https://doi.org/10.1109/MTDT.2003.1222359","url":null,"abstract":"The exact placement of the data output eye for high speed single and double data rate (SDR, DDR) synchronous dynamic random access memories (SDRAM) allows high speed operation. For the timing measurement method via current presented in this paper the tester drives data at the same time as the device. The current consumption of the device is depending on the overlap of the tester output waveform and the waveform of the data driven by the device under test (DUT). This paper presents the measurement method and results from a 128M x4 SDRAM and compares them to a traditional approach using a data strobe.","PeriodicalId":412381,"journal":{"name":"Records of the 2003 International Workshop on Memory Technology, Design and Testing","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134297487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-28DOI: 10.1109/MTDT.2003.1222365
J. Daga, Caroline Papaix, E. Racape, M. Combe, Vincent Sialelli, J. Guichaoua
2Mbits EEPROM memory has been designed using the ATMEL 0.18 /spl mu/m embedded technology. On silicon program and read access time measurements are given, and an optimized production testing flow is proposed.
{"title":"A 40 ns random access time low voltage 2Mbits EEPROM memory for embedded applications","authors":"J. Daga, Caroline Papaix, E. Racape, M. Combe, Vincent Sialelli, J. Guichaoua","doi":"10.1109/MTDT.2003.1222365","DOIUrl":"https://doi.org/10.1109/MTDT.2003.1222365","url":null,"abstract":"2Mbits EEPROM memory has been designed using the ATMEL 0.18 /spl mu/m embedded technology. On silicon program and read access time measurements are given, and an optimized production testing flow is proposed.","PeriodicalId":412381,"journal":{"name":"Records of the 2003 International Workshop on Memory Technology, Design and Testing","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126717966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-28DOI: 10.1109/MTDT.2003.1222366
D. Salamon, B. Cockburn
Chalcogenide glass is being investigated by several companies as the basis for a scalable and embeddable nonvolatile phase-change memory technology. One phase is a high-resistance amorphous phase that is obtained by melting a small volume of glass using ohmic heating, and then quenching it. The second phase is a low-resistance crystalline phase that is obtained by heating the glass to just below the melting point to promote recrystallization. This paper describes two models for such a cell. The first is a very simple single-element, lumped model that exhibits correct phase transition behavior, but is unrealistic in its sensitivity to the heating current pulses. The second, multiple-element model is able to more realistically represent cell heating and cooling behavior, and appears to be the more suitable basis for an electrical simulation model.
{"title":"An electrical simulation model for the chalcogenide phase-change memory cell","authors":"D. Salamon, B. Cockburn","doi":"10.1109/MTDT.2003.1222366","DOIUrl":"https://doi.org/10.1109/MTDT.2003.1222366","url":null,"abstract":"Chalcogenide glass is being investigated by several companies as the basis for a scalable and embeddable nonvolatile phase-change memory technology. One phase is a high-resistance amorphous phase that is obtained by melting a small volume of glass using ohmic heating, and then quenching it. The second phase is a low-resistance crystalline phase that is obtained by heating the glass to just below the melting point to promote recrystallization. This paper describes two models for such a cell. The first is a very simple single-element, lumped model that exhibits correct phase transition behavior, but is unrealistic in its sensitivity to the heating current pulses. The second, multiple-element model is able to more realistically represent cell heating and cooling behavior, and appears to be the more suitable basis for an electrical simulation model.","PeriodicalId":412381,"journal":{"name":"Records of the 2003 International Workshop on Memory Technology, Design and Testing","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133052421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-28DOI: 10.1109/MTDT.2003.1222355
B. Cockburn, J.H. Tapia, D. Elliott
We propose a multilevel DRAM (MLDRAM) with serial sensing that has lower area overhead than designs that use single-step, flash conversion sensing. The new design exploits hierarchical, multidivided bitlines to offset the reduction in noise margins caused by multilevel signaling and thereby better preserve the signal-to-noise ratio. The multiple sensing operations required to recover multilevel data are performed serially to re-use sense amplifiers and hence minimize the area overhead of the peripheral circuitry at the cost of increased total read time. In a variation of the proposed design, a subset of the addressed row of cells is read in one sensing step while the remaining cells are recovered later in further sensing steps.
{"title":"A multilevel DRAM with hierarchical bitlines and serial sensing","authors":"B. Cockburn, J.H. Tapia, D. Elliott","doi":"10.1109/MTDT.2003.1222355","DOIUrl":"https://doi.org/10.1109/MTDT.2003.1222355","url":null,"abstract":"We propose a multilevel DRAM (MLDRAM) with serial sensing that has lower area overhead than designs that use single-step, flash conversion sensing. The new design exploits hierarchical, multidivided bitlines to offset the reduction in noise margins caused by multilevel signaling and thereby better preserve the signal-to-noise ratio. The multiple sensing operations required to recover multilevel data are performed serially to re-use sense amplifiers and hence minimize the area overhead of the peripheral circuitry at the cost of increased total read time. In a variation of the proposed design, a subset of the addressed row of cells is read in one sensing step while the remaining cells are recovered later in further sensing steps.","PeriodicalId":412381,"journal":{"name":"Records of the 2003 International Workshop on Memory Technology, Design and Testing","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130864909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-28DOI: 10.1109/MTDT.2003.1222361
Rei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu, Jin-Fu Li
Memory cores (especially SRAM cores) used on a system chip usually come from a memory compiler. Commercial memory compilers have their limitation-a large memory may need to be implemented with multiple small memories, if generated by memory compilers. In this paper we introduce a testability-driven memory optimizer and wrapper generator that generates BISTed embedded memories by using a commercial memory compiler. We describe one of its key components called MORE (for Memory Optimization and REconfiguration). The approach is cost effective for designing embedded memories. By configuring small memory cores into the large one specified by the user and providing the BIST circuits, MORE allows the user to combine the commercial memory compiler and our memory BIST compiler into a cost-effective testability-driven memory generator. The resulting memory has a shorter test time, since the small memory cores can be tested in parallel, so far as the power and geometry constraints are considered. As an example, the test time of a typical 256 K/spl times/32 memory generated by MORE is reduced by about 75%.
{"title":"A testability-driven optimizer and wrapper generator for embedded memories","authors":"Rei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu, Jin-Fu Li","doi":"10.1109/MTDT.2003.1222361","DOIUrl":"https://doi.org/10.1109/MTDT.2003.1222361","url":null,"abstract":"Memory cores (especially SRAM cores) used on a system chip usually come from a memory compiler. Commercial memory compilers have their limitation-a large memory may need to be implemented with multiple small memories, if generated by memory compilers. In this paper we introduce a testability-driven memory optimizer and wrapper generator that generates BISTed embedded memories by using a commercial memory compiler. We describe one of its key components called MORE (for Memory Optimization and REconfiguration). The approach is cost effective for designing embedded memories. By configuring small memory cores into the large one specified by the user and providing the BIST circuits, MORE allows the user to combine the commercial memory compiler and our memory BIST compiler into a cost-effective testability-driven memory generator. The resulting memory has a shorter test time, since the small memory cores can be tested in parallel, so far as the power and geometry constraints are considered. As an example, the test time of a typical 256 K/spl times/32 memory generated by MORE is reduced by about 75%.","PeriodicalId":412381,"journal":{"name":"Records of the 2003 International Workshop on Memory Technology, Design and Testing","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115305778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-28DOI: 10.1109/MTDT.2003.1222360
Baosheng Wang, Josh Yang, A. Ivanov
Compared with traditional functional fault models, fault model obtained from an Inductive Fault Analysis (IFA) test flow can provide an attractive basis for obtaining a good estimate of the overall test quality in terms of defect level and yield. However, the associated surging test time due to increased SRAM capacity is becoming a major challenge when testing either standalone or embedded SRAMs. This paper refines the functional fault models translated from defect simulations for embedded SRAMs with IFA proposed and described. Reconsidering the defect causes of the functional faults allows us to simplify the functional fault model FFM2 and formulate the test time required for detecting Data Retention Faults. We combine this simplification with the consideration of specific memory redundancy elements to develop a new March 6N Test algorithm. Simulation results reveal that our proposed fault modeling and test generation algorithm can reduce total test time to one half or less of that required by the methodology, while maintaining the same defect and fault coverage.
{"title":"Reducing test time of embedded SRAMs","authors":"Baosheng Wang, Josh Yang, A. Ivanov","doi":"10.1109/MTDT.2003.1222360","DOIUrl":"https://doi.org/10.1109/MTDT.2003.1222360","url":null,"abstract":"Compared with traditional functional fault models, fault model obtained from an Inductive Fault Analysis (IFA) test flow can provide an attractive basis for obtaining a good estimate of the overall test quality in terms of defect level and yield. However, the associated surging test time due to increased SRAM capacity is becoming a major challenge when testing either standalone or embedded SRAMs. This paper refines the functional fault models translated from defect simulations for embedded SRAMs with IFA proposed and described. Reconsidering the defect causes of the functional faults allows us to simplify the functional fault model FFM2 and formulate the test time required for detecting Data Retention Faults. We combine this simplification with the consideration of specific memory redundancy elements to develop a new March 6N Test algorithm. Simulation results reveal that our proposed fault modeling and test generation algorithm can reduce total test time to one half or less of that required by the methodology, while maintaining the same defect and fault coverage.","PeriodicalId":412381,"journal":{"name":"Records of the 2003 International Workshop on Memory Technology, Design and Testing","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128836452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-28DOI: 10.1109/MTDT.2003.1222356
Y. Zenda, K. Nakamae, H. Fujioka
We study on cost optimum embedded DRAM interconnect technologies by using a simple VLSI particle-induced fault simulator modified for the embedded DRAM macro. The fault simulator is applied to an assumed 4-Mbit DRAM macro production process with DRAM interconnect technologies of DRAM 1/2 pitch 115 nm and ASIC 1/2 pitch of from 115 nm to 500 nm (peripheral circuits). The DRAM macro is included in a SoC chip that has area of 1 cm/sup 2/ and is manufactured on the wafer with size of 8 inches. Result shows that the wider pitch decreases the count of manufactured chips but increases the yield. ASIC 1/2 pitch of 0.4 /spl mu/m achieved maximum count of good chips per wafer under the assumed conditions. There exists the cost optimum embedded DRAM design.
{"title":"Cost optimum embedded DRAM design by yield analysis","authors":"Y. Zenda, K. Nakamae, H. Fujioka","doi":"10.1109/MTDT.2003.1222356","DOIUrl":"https://doi.org/10.1109/MTDT.2003.1222356","url":null,"abstract":"We study on cost optimum embedded DRAM interconnect technologies by using a simple VLSI particle-induced fault simulator modified for the embedded DRAM macro. The fault simulator is applied to an assumed 4-Mbit DRAM macro production process with DRAM interconnect technologies of DRAM 1/2 pitch 115 nm and ASIC 1/2 pitch of from 115 nm to 500 nm (peripheral circuits). The DRAM macro is included in a SoC chip that has area of 1 cm/sup 2/ and is manufactured on the wafer with size of 8 inches. Result shows that the wider pitch decreases the count of manufactured chips but increases the yield. ASIC 1/2 pitch of 0.4 /spl mu/m achieved maximum count of good chips per wafer under the assumed conditions. There exists the cost optimum embedded DRAM design.","PeriodicalId":412381,"journal":{"name":"Records of the 2003 International Workshop on Memory Technology, Design and Testing","volume":"80 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132236836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-28DOI: 10.1109/MTDT.2003.1222357
Z. Al-Ars, A. V. Goor
The high complexity of the faulty behavior observed in DRAMs is caused primarily by the presence of internal floating nodes in defective DRAMs. This paper describes a new analysis method to apply electrical simulation for investigating the faulty behavior resulting from defects causing two floating nodes within the memory. The paper also presents the results of a simulation study performed on bit line opens to validate the newly proposed method, and suggests a test to detect these bit line opens.
{"title":"Systematic memory test generation for DRAM defects causing two floating nodes","authors":"Z. Al-Ars, A. V. Goor","doi":"10.1109/MTDT.2003.1222357","DOIUrl":"https://doi.org/10.1109/MTDT.2003.1222357","url":null,"abstract":"The high complexity of the faulty behavior observed in DRAMs is caused primarily by the presence of internal floating nodes in defective DRAMs. This paper describes a new analysis method to apply electrical simulation for investigating the faulty behavior resulting from defects causing two floating nodes within the memory. The paper also presents the results of a simulation study performed on bit line opens to validate the newly proposed method, and suggests a test to detect these bit line opens.","PeriodicalId":412381,"journal":{"name":"Records of the 2003 International Workshop on Memory Technology, Design and Testing","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116476939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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