A 2.4 μm CMOS switched-capacitor video decimator with sampling rate reduction from 40.5 MHz to 13.5 MHz

1989 Proceedings of the IEEE Custom Integrated Circuits Conference Pub Date : 1989-05-15 DOI:10.1109/CICC.1989.56831

R. Martins, J. Franca

引用次数: 16

Abstract

A description is given of the design and integrated-circuit implementation of a fifth-order elliptic lowpass switched-capacitor (SC) video decimator with a cutoff frequency of 3.6 MHz and sampling rate reduction from 40.5 MHz to 13.5 MHz. A recently proposed decimator architecture used to make the settling time requirements of the operational amplifiers similar to those of a conventional SC filter with switching frequency of only 13.5 MHz. The circuit is implemented using a 2.4-μm CMOS double-poly process yielding a total area of less than 1 mm2. The power consumption is less than 50 mW with a 10-V power supply

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2.4 μ m CMOS开关电容视频抽取器，采样率从40.5 MHz降至13.5 MHz

介绍了一种截止频率为3.6 MHz、采样率从40.5 MHz降至13.5 MHz的五阶椭圆低通开关电容(SC)视频抽取器的设计和集成电路实现。最近提出了一种十进制结构，用于使运算放大器的稳定时间要求类似于传统的SC滤波器，开关频率仅为13.5 MHz。该电路采用2.4 μm CMOS双聚工艺实现，总面积小于1 mm2。10v供电时，功耗小于50mw

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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1989 Proceedings of the IEEE Custom Integrated Circuits Conference

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