Test structures for CMOS RF reliability assessment

Abstract

This work presents an improved methodology for CMOS RF reliability assessment with on-chip AC stress circuits. Compared to previous work high frequency stress signals are not only generated on-chip, but are also monitored by an on-chip oscilloscope (OCO). Experimental data from a HKMG technology highlight that without the OCO, existing test structures often lead to misinterpreted results under AC and RF stress.