Pub Date : 2016-05-23DOI: 10.1109/ICMTS.2016.7476198
E. Blair, D. Corrigan, I. Schmueser, J. Terry, Stewart Smith, Andrew R. Mount, Anthony J. Walton
This paper reports the design and application of test structures used for the development and characterisation of microelectrodes for operation in the harsh, caustic environment of molten salts operating at 450°C. These structures have been employed to evaluate the effect of electrode area and the dielectric integrity of insulating layers in the molten salt. This has been useful in identifying failures mechanisms, which has facilitated the optimisation of both the design and fabrication of the microelectrodes while at the same time also providing valuable information for process verification.
{"title":"Test structures to support the development and process verification of microelectrodes for high temperature operation in molten salts","authors":"E. Blair, D. Corrigan, I. Schmueser, J. Terry, Stewart Smith, Andrew R. Mount, Anthony J. Walton","doi":"10.1109/ICMTS.2016.7476198","DOIUrl":"https://doi.org/10.1109/ICMTS.2016.7476198","url":null,"abstract":"This paper reports the design and application of test structures used for the development and characterisation of microelectrodes for operation in the harsh, caustic environment of molten salts operating at 450°C. These structures have been employed to evaluate the effect of electrode area and the dielectric integrity of insulating layers in the molten salt. This has been useful in identifying failures mechanisms, which has facilitated the optimisation of both the design and fabrication of the microelectrodes while at the same time also providing valuable information for process verification.","PeriodicalId":344487,"journal":{"name":"2016 International Conference on Microelectronic Test Structures (ICMTS)","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123596430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-23DOI: 10.1109/ICMTS.2016.7476193
Y. Shuto, Shuu'ichirou Yamamoto, S. Sugahara
Power-gating (PG) architectures employing nonvolatile state/data retention are expected to be a highly efficient energy reduction technique for high-performance CMOS logic systems. Recently, two types of PG architectures using nonvolatile retention have been proposed: One architecture is nonvolatile PG (NVPG) using nonvolatile bistable circuits such as nonvolatile SRAM (NV-SRAM) and nonvolatile flip-flop (NV-FF), in which nonvolatile retention is not utilized during the normal SRAM/FF operation mode and it is used only when there exist energetically meaningful shutdown periods given by break-even time (BET). In contrast, the other architecture employs nonvolatile retention during the normal SRAM/FF operation mode. In this type of architecture, an even short standby period can be replaced by a shutdown period, and thus this architecture is also called normally-off (NOF) rather than PG. In this paper, these two PG architectures for a FinFET-based high-performance NV-SRAM cell employing spintronics-based nonvolatile retention were systematically analyzed using HSPICE with a magnetoresistive-device macromodel. The NVPG architecture shows effective reduction of energy dissipation without performance degradation, whereas the NOF architecture causes severe performance degradation and the energy efficiency of the NOF architecture cannot be superior to that of the NVPG architecture.
{"title":"New power-gating architectures using nonvolatile retention: Comparative study of nonvolatile power-gating (NVPG) and normally-off architectures for SRAM","authors":"Y. Shuto, Shuu'ichirou Yamamoto, S. Sugahara","doi":"10.1109/ICMTS.2016.7476193","DOIUrl":"https://doi.org/10.1109/ICMTS.2016.7476193","url":null,"abstract":"Power-gating (PG) architectures employing nonvolatile state/data retention are expected to be a highly efficient energy reduction technique for high-performance CMOS logic systems. Recently, two types of PG architectures using nonvolatile retention have been proposed: One architecture is nonvolatile PG (NVPG) using nonvolatile bistable circuits such as nonvolatile SRAM (NV-SRAM) and nonvolatile flip-flop (NV-FF), in which nonvolatile retention is not utilized during the normal SRAM/FF operation mode and it is used only when there exist energetically meaningful shutdown periods given by break-even time (BET). In contrast, the other architecture employs nonvolatile retention during the normal SRAM/FF operation mode. In this type of architecture, an even short standby period can be replaced by a shutdown period, and thus this architecture is also called normally-off (NOF) rather than PG. In this paper, these two PG architectures for a FinFET-based high-performance NV-SRAM cell employing spintronics-based nonvolatile retention were systematically analyzed using HSPICE with a magnetoresistive-device macromodel. The NVPG architecture shows effective reduction of energy dissipation without performance degradation, whereas the NOF architecture causes severe performance degradation and the energy efficiency of the NOF architecture cannot be superior to that of the NVPG architecture.","PeriodicalId":344487,"journal":{"name":"2016 International Conference on Microelectronic Test Structures (ICMTS)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126429641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-20DOI: 10.1109/ICMTS.2016.7476183
Chun-Yu Lin, Rong-Kun Chang
The test structures of inductor-assisted silicon-controlled rectifier (LASCR) are investigated in this work to protect the radio-frequency (RF) integrated circuits from electrostatic discharge (ESD) damages. Verified in silicon chip, the LASCR with the assistance of inductor can provide both good ESD robustness and RF performances. With the better performances, the LASCR is very suitable for gigahertz RF applications.
{"title":"Test structures of LASCR device for RF ESD protection in nanoscale CMOS process","authors":"Chun-Yu Lin, Rong-Kun Chang","doi":"10.1109/ICMTS.2016.7476183","DOIUrl":"https://doi.org/10.1109/ICMTS.2016.7476183","url":null,"abstract":"The test structures of inductor-assisted silicon-controlled rectifier (LASCR) are investigated in this work to protect the radio-frequency (RF) integrated circuits from electrostatic discharge (ESD) damages. Verified in silicon chip, the LASCR with the assistance of inductor can provide both good ESD robustness and RF performances. With the better performances, the LASCR is very suitable for gigahertz RF applications.","PeriodicalId":344487,"journal":{"name":"2016 International Conference on Microelectronic Test Structures (ICMTS)","volume":"181 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125192986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-29DOI: 10.1109/ICMTS.2016.7476204
S. Scarfi, Stewart Smith, A. Tabašnikov, Ilka Schmüser, E. Blair, Andrew Bunting, Anthony J. Walton, Alan F. Murray, J. Terry
Conductive carbon films are highly attractive for use as electrodes in electrochemistry and biosensing applications. Patterned photoresist films can be transformed into carbon electrodes using standard photolithographic techniques followed by pyrolysation of the photoresist in a furnace under a reducing atmosphere. Previous studies have been made of the electrical properties of blanket carbon films created using this method of fabrication. However, there is a need to investigate pattern dependent effects, particularly the extent to which the dimensions of the patterned films shrink during the high temperature processing. This study applies microfabricated test structures to the process characterisation of conductive carbon produced from standard positive photoresists.
{"title":"Test structures for the characterisation of conductive carbon produced from photoresist","authors":"S. Scarfi, Stewart Smith, A. Tabašnikov, Ilka Schmüser, E. Blair, Andrew Bunting, Anthony J. Walton, Alan F. Murray, J. Terry","doi":"10.1109/ICMTS.2016.7476204","DOIUrl":"https://doi.org/10.1109/ICMTS.2016.7476204","url":null,"abstract":"Conductive carbon films are highly attractive for use as electrodes in electrochemistry and biosensing applications. Patterned photoresist films can be transformed into carbon electrodes using standard photolithographic techniques followed by pyrolysation of the photoresist in a furnace under a reducing atmosphere. Previous studies have been made of the electrical properties of blanket carbon films created using this method of fabrication. However, there is a need to investigate pattern dependent effects, particularly the extent to which the dimensions of the patterned films shrink during the high temperature processing. This study applies microfabricated test structures to the process characterisation of conductive carbon produced from standard positive photoresists.","PeriodicalId":344487,"journal":{"name":"2016 International Conference on Microelectronic Test Structures (ICMTS)","volume":"99 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120930817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-28DOI: 10.1109/ICMTS.2016.7476205
X. Liu, L. Nanver
A 2-diode test structure is proposed and investigated for use with simple I-V measurements, giving an easy-to-process, fast turn-around-time method of comparing process-dependent current flows when developing ultrashallow/ Schottky junction technologies. Differential diode current characteristics and collector currents obtained from lateral transistor operation of the same 2-diode test structure are used to reliably identify the diode type and variations in metal-Si interfacial properties, independent of parasitic leakage currents. The versatility of this method with respect to diode geometry and substrate doping is verified for the measurement of junction- and Schottky-like diodes formed by different chemical-vapor-deposition processes.
{"title":"Comparing current flows in ultrashallow pn-/Schottky-like diodes with 2-diode test method","authors":"X. Liu, L. Nanver","doi":"10.1109/ICMTS.2016.7476205","DOIUrl":"https://doi.org/10.1109/ICMTS.2016.7476205","url":null,"abstract":"A 2-diode test structure is proposed and investigated for use with simple I-V measurements, giving an easy-to-process, fast turn-around-time method of comparing process-dependent current flows when developing ultrashallow/ Schottky junction technologies. Differential diode current characteristics and collector currents obtained from lateral transistor operation of the same 2-diode test structure are used to reliably identify the diode type and variations in metal-Si interfacial properties, independent of parasitic leakage currents. The versatility of this method with respect to diode geometry and substrate doping is verified for the measurement of junction- and Schottky-like diodes formed by different chemical-vapor-deposition processes.","PeriodicalId":344487,"journal":{"name":"2016 International Conference on Microelectronic Test Structures (ICMTS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124979176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-28DOI: 10.1109/ICMTS.2016.7476187
K. Takano, M. Goto, E. Shiling, A. Gasasira, J. Liao
Direct Charge Measurement (DCM) has a capability to improve the capacitance measurement time in parametric test. Through an actual wafer measurement, we have successfully verified that DCM can measure MOS capacitor much faster than an LCR meter while keeping good correlations for wafer manufacturing.
{"title":"Demonstration of MOS capacitor measurement for wafer manufacturing using a Direct Charge Measurement","authors":"K. Takano, M. Goto, E. Shiling, A. Gasasira, J. Liao","doi":"10.1109/ICMTS.2016.7476187","DOIUrl":"https://doi.org/10.1109/ICMTS.2016.7476187","url":null,"abstract":"Direct Charge Measurement (DCM) has a capability to improve the capacitance measurement time in parametric test. Through an actual wafer measurement, we have successfully verified that DCM can measure MOS capacitor much faster than an LCR meter while keeping good correlations for wafer manufacturing.","PeriodicalId":344487,"journal":{"name":"2016 International Conference on Microelectronic Test Structures (ICMTS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128437166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-28DOI: 10.1109/ICMTS.2016.7476200
J. Tsai, R. Chang, Cheng-Hui Chou, Hsueh-Chun Liao, S. Huang, Sung-Hung Lin, Jui-Chang Lin
This work focuses on the development of a novel test structure to evaluate the dynamic behavior of electrical characteristics in the boron-implanted germanium samples during the solid phase epitaxial regrowth (SPER) at low temperature annealing of 360 and 400 °C with various annealing times ranging from 30 to 300 min. In the early stage of SPER annealing, the sheet carrier concentration is increased with annealing time. And then, it will saturate to a level after about 2 hr annealing which implies the completion of SPER process.
{"title":"Novel test structure for evaluating dynamic dopant activation after ion implantation","authors":"J. Tsai, R. Chang, Cheng-Hui Chou, Hsueh-Chun Liao, S. Huang, Sung-Hung Lin, Jui-Chang Lin","doi":"10.1109/ICMTS.2016.7476200","DOIUrl":"https://doi.org/10.1109/ICMTS.2016.7476200","url":null,"abstract":"This work focuses on the development of a novel test structure to evaluate the dynamic behavior of electrical characteristics in the boron-implanted germanium samples during the solid phase epitaxial regrowth (SPER) at low temperature annealing of 360 and 400 °C with various annealing times ranging from 30 to 300 min. In the early stage of SPER annealing, the sheet carrier concentration is increased with annealing time. And then, it will saturate to a level after about 2 hr annealing which implies the completion of SPER process.","PeriodicalId":344487,"journal":{"name":"2016 International Conference on Microelectronic Test Structures (ICMTS)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131955775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-28DOI: 10.1109/ICMTS.2016.7476190
Hao Qiu, K. Takeuchi, T. Mizutani, T. Saraya, M. Kobayashi, T. Hiramoto
A new extended write butterfly curve (BC) is proposed and evaluated through our device-matrix-array test-element-group (DMA-TEG) fabricated by Silicon-on-Thin-BOX (SOTB) technology. A good normality at low supply voltage (VDD), as well as good correlation with word-line method, demonstrates the extended write BC as a good candidate for yield estimation at low VDD. The comparison with conventional write BC is also discussed.
{"title":"A new write stability metric using extended write butterfly curve for yield estimation in SRAM cells at low supply voltage","authors":"Hao Qiu, K. Takeuchi, T. Mizutani, T. Saraya, M. Kobayashi, T. Hiramoto","doi":"10.1109/ICMTS.2016.7476190","DOIUrl":"https://doi.org/10.1109/ICMTS.2016.7476190","url":null,"abstract":"A new extended write butterfly curve (BC) is proposed and evaluated through our device-matrix-array test-element-group (DMA-TEG) fabricated by Silicon-on-Thin-BOX (SOTB) technology. A good normality at low supply voltage (VDD), as well as good correlation with word-line method, demonstrates the extended write BC as a good candidate for yield estimation at low VDD. The comparison with conventional write BC is also discussed.","PeriodicalId":344487,"journal":{"name":"2016 International Conference on Microelectronic Test Structures (ICMTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130015956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-28DOI: 10.1109/ICMTS.2016.7476175
H. Tuinhout, R. van Dalen
This paper discusses a 2100-DUT-array based test structure approach for high-resolution characterization of spatial mechanical stress distributions that are attributable to wafer level chip scale package solder bumps. DUT cell layout requirements, array implementation, measurement approach, and some data analysis challenges are reviewed in detail. Several examples of solder bump induced mobility variation illustrate the value of these test structures.
{"title":"Design and use of an array-based test structure to characterize mechanical stress effects caused by WLCSP solder bumps","authors":"H. Tuinhout, R. van Dalen","doi":"10.1109/ICMTS.2016.7476175","DOIUrl":"https://doi.org/10.1109/ICMTS.2016.7476175","url":null,"abstract":"This paper discusses a 2100-DUT-array based test structure approach for high-resolution characterization of spatial mechanical stress distributions that are attributable to wafer level chip scale package solder bumps. DUT cell layout requirements, array implementation, measurement approach, and some data analysis challenges are reviewed in detail. Several examples of solder bump induced mobility variation illustrate the value of these test structures.","PeriodicalId":344487,"journal":{"name":"2016 International Conference on Microelectronic Test Structures (ICMTS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130871206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-03-28DOI: 10.1109/ICMTS.2016.7476185
S. Mori, K. Sawada, Manabu Tomita, K. Ogawa, Tsuyoshi Suzuki, H. Oishi, M. Bairo, Y. Fukuzaki, H. Ohnuma
A highly effective and versatile test structure with a flexible pulse generating circuit is proposed. Several significant features of the key components are demonstrated, that is, the tunable ring oscillator, the start-stop pulse controller, the Charge Injection induced Error Free Charge Based Capacitance Measurement (CIEF-CBCM) using Self-Aligned pulses and the modified Charge Pumping (CP) technique. This circuit system enables efficiently to collect data of multiple dielectric properties.
{"title":"Highly effective and versatile test structure for evaluating dielectric properties using flexible pulse generator on chip","authors":"S. Mori, K. Sawada, Manabu Tomita, K. Ogawa, Tsuyoshi Suzuki, H. Oishi, M. Bairo, Y. Fukuzaki, H. Ohnuma","doi":"10.1109/ICMTS.2016.7476185","DOIUrl":"https://doi.org/10.1109/ICMTS.2016.7476185","url":null,"abstract":"A highly effective and versatile test structure with a flexible pulse generating circuit is proposed. Several significant features of the key components are demonstrated, that is, the tunable ring oscillator, the start-stop pulse controller, the Charge Injection induced Error Free Charge Based Capacitance Measurement (CIEF-CBCM) using Self-Aligned pulses and the modified Charge Pumping (CP) technique. This circuit system enables efficiently to collect data of multiple dielectric properties.","PeriodicalId":344487,"journal":{"name":"2016 International Conference on Microelectronic Test Structures (ICMTS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122134589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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