{"title":"A 6 nsec CMOS EPLD with μW standby power","authors":"M. J. Allen","doi":"10.1109/CICC.1989.56689","DOIUrl":null,"url":null,"abstract":"A description is presented of a 28-pin CMOS EPROM (erasable programmable read-only memory)-based programmable logic device optimized for memory-address-decoding applications. A novel architecture provides high-speed operation at CMOS power levels. Reprogrammability and 100% testability of EPROM technology are added benefits. Active power is less than 25% of slower bipolar solutions, and die area is 74 mil2","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"51 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1989.56689","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A description is presented of a 28-pin CMOS EPROM (erasable programmable read-only memory)-based programmable logic device optimized for memory-address-decoding applications. A novel architecture provides high-speed operation at CMOS power levels. Reprogrammability and 100% testability of EPROM technology are added benefits. Active power is less than 25% of slower bipolar solutions, and die area is 74 mil2
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