{"title":"SCAN - Secure Processor","authors":"R. Kannavara, N. Bourbakis, A. Dollas, P. Athanas","doi":"10.1109/NAECON.2008.4806549","DOIUrl":null,"url":null,"abstract":"This paper presents the design of the SCAN secure processor. The SCAN secure processor is a modified SparcV8 processor architecture offering a SCAN-based encryption and decryption of 32 bit instructions and data. We further discuss the evaluation of the proposed SCAN-SP architecture with certain simulated benchmark applications.","PeriodicalId":254758,"journal":{"name":"2008 IEEE National Aerospace and Electronics Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE National Aerospace and Electronics Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NAECON.2008.4806549","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
This paper presents the design of the SCAN secure processor. The SCAN secure processor is a modified SparcV8 processor architecture offering a SCAN-based encryption and decryption of 32 bit instructions and data. We further discuss the evaluation of the proposed SCAN-SP architecture with certain simulated benchmark applications.
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