Silicon-on-insulator dynamic threshold ESD networks and active clamp circuitry

Abstract

Active clamp circuits are key to minimize electrical overshoot and undershoot and minimize reflected signals and achieve performance objectives and reliability requirements in high performance CMOS circuits. This paper discusses for the first time the electrostatic discharge (ESD) protection circuits of silicon-on-insulator (SOI) active clamp networks, dynamic threshold MOSFET SOI ESD techniques and the synthesis of DTMOS concepts, ESD protection networks, and active clamp circuitry for high-pin-count high-performance semiconductor chips.