1T1MTJ STT-MRAM Cell Array Design with an Adaptive Reference Voltage Generator for Improving Device Variation Tolerance

Abstract

A device-variation-tolerant spin-transfer-torque magnetic random access memory (STT-MRAM) cell array design with a high-signal-margin reference generator circuit was developed to create high-density 1T1MTJ STT-MRAMs. To realize an appropriate STT-MRAM design, fluctuations in the memory cell characteristics were first measured using a 1-kbit STT-MRAM test chip. Based on these measurements, a reference generator and an STT-MRAM cell array architecture were proposed. This cell array was evaluated in terms of the signal margin for read operation and its tolerance to device variation by means of Monte-Carlo SPICE circuit simulations. The proposed design enables a 50% improvement in the signal margin compared with the conventional cell array circuit.