Functional failure analysis of logic LSIs from backside of the chip and its verification by logic simulation

Abstract

A novel technique has been developed for fault isolation in logic LSIs. The technique is constructed using backside infra-red light detection through the silicon chip by an emission microscope, which is connected to an automated test equipment (ATE), and linked to a CAD layout pattern view system which assists the chip backside image and logic simulation for fault verification. This technique can perform an exact functional failure analysis from the backside of the chip.