Soyeon Kim, Byeonghyeon Kim, Yongho Lee, Seungsoo Kim, Hyunchol Shin
{"title":"A 28GHz Direct Conversion Receiver in 65nm CMOS for 5G mmWave Radio","authors":"Soyeon Kim, Byeonghyeon Kim, Yongho Lee, Seungsoo Kim, Hyunchol Shin","doi":"10.1109/isocc47750.2019.9027756","DOIUrl":null,"url":null,"abstract":"This paper presents a direct-conversion zero-IF receiver front-end circuit for 28-GHz 5G mobile communications. The RF receiver is composed of LNA, quadrature downconversion mixer, wideband 50-ohm driving buffer, and I/Q generation LO buffer. The low-noise amplifier is designed in two-stage, in which the first cascode stage performs the single-to-differential conversion by using a transformer load. The mixer is a gilbert-cell active type. The 50-ohm driving buffer performs the differential-to-single conversion for test interface purpose. An external LO signal is fed to a RC polyphase filter, and splits into differential I/Q LO signals. Designed in 65nm CMOS process, extensive electromagnetic simulations after chip layout are carried out to evaluate the performances. The full receiver dissipates 90 mW from a 1.2-V supply. The Rx full-path gives the gain of +27.4 dB, noise figure of 4.6 dB, 1-dB input compression point of -38 dBm, and the baseband channel bandwidth of 1 GHz. The die size is 2 mm2including RF pads.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/isocc47750.2019.9027756","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
This paper presents a direct-conversion zero-IF receiver front-end circuit for 28-GHz 5G mobile communications. The RF receiver is composed of LNA, quadrature downconversion mixer, wideband 50-ohm driving buffer, and I/Q generation LO buffer. The low-noise amplifier is designed in two-stage, in which the first cascode stage performs the single-to-differential conversion by using a transformer load. The mixer is a gilbert-cell active type. The 50-ohm driving buffer performs the differential-to-single conversion for test interface purpose. An external LO signal is fed to a RC polyphase filter, and splits into differential I/Q LO signals. Designed in 65nm CMOS process, extensive electromagnetic simulations after chip layout are carried out to evaluate the performances. The full receiver dissipates 90 mW from a 1.2-V supply. The Rx full-path gives the gain of +27.4 dB, noise figure of 4.6 dB, 1-dB input compression point of -38 dBm, and the baseband channel bandwidth of 1 GHz. The die size is 2 mm2including RF pads.