Interfacing test equipment to high density chip-on-tape

Third Annual IEEE Proceedings on ASIC Seminar and Exhibit Pub Date : 1990-09-17 DOI:10.1109/ASIC.1990.186178

R. Nelson, B. Williams, G. Westbrook

引用次数: 0

Abstract

Test hardware interface requirements for testing high-pin-count ASIC TAB (tape automated bonding) products are discussed. Test solutions which have been proven in a production environment are described. Test-on-tape using the techniques illustrated has proven viable for high-speed bipolar gate arrays having 360 leads with 0.004 in lead width and 0.008 in lead pitch in the (outer lead bond) and test area. Successfully testing small pitch outer leads of TAB products requires the combination of electrical, mechanical, and thermal designs to be controlled within specific tolerances. The final testing of TAB ASICs is performed after all other value added processes have been completed. Therefore, an understanding of the factors which impact final test yield is essential.<>

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将测试设备连接到高密度的磁带上芯片

讨论了测试高引脚数ASIC TAB(磁带自动粘合)产品的测试硬件接口要求。描述了在生产环境中经过验证的测试解决方案。使用所示技术的磁带测试已被证明适用于具有360个引线的高速双极栅极阵列，引线宽度为0.004，引线间距为0.008(外引线键)和测试区域。成功测试TAB产品的小间距外引线需要结合电气，机械和热设计，将其控制在特定的公差范围内。TAB asic的最终测试是在所有其他增值过程完成后进行的。因此，了解影响最终试验良率的因素是至关重要的。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Third Annual IEEE Proceedings on ASIC Seminar and Exhibit

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